专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07803692B2 Manufacturing method of semiconductor device having self-aligned contact 有权
标题翻译：具有自对准接触的半导体器件的制造方法
公开(公告)号：US07803692B2
公开(公告)日：2010-09-28
申请号：US12562142
申请日：2009-09-18
申请人： Min-San Huang , Hann-Jye Hsu , Yung-Chung Yao
发明人： Min-San Huang , Hann-Jye Hsu , Yung-Chung Yao
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.
摘要翻译：提供一种制造具有自对准触点的半导体器件的方法。在衬底上形成多个隔离结构以限定有源区。在基板上形成多个栅极结构。在每个栅极结构旁边的衬底中形成多个掺杂区域。在每个栅极结构的侧壁上形成多个第一间隔物。多个第二间隔件形成在每个隔离结构的侧壁上。在基板上形成电介质层。然后，进行自对准工艺以在栅极结构之间的介电层中形成多个接触开口。导电材料填充在接触开口中。

2. 发明申请

US20100003796A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACT 有权
标题翻译：具有自对准接触的半导体器件的制造方法
公开(公告)号：US20100003796A1
公开(公告)日：2010-01-07
申请号：US12562142
申请日：2009-09-18
申请人： Min-San Huang , Hann-Jye Hsu , Yung-Chung Yao
发明人： Min-San Huang , Hann-Jye Hsu , Yung-Chung Yao
IPC分类号： H01L21/77
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.
摘要翻译：提供一种制造具有自对准触点的半导体器件的方法。在衬底上形成多个隔离结构以限定有源区。在基板上形成多个栅极结构。在每个栅极结构旁边的衬底中形成多个掺杂区域。在每个栅极结构的侧壁上形成多个第一间隔物。多个第二间隔件形成在每个隔离结构的侧壁上。在基板上形成电介质层。然后，进行自对准工艺以在栅极结构之间的介电层中形成多个接触开口。导电材料填充在接触开口中。

3. 发明授权

US07575027B2 Weave with visual color variation 有权
标题翻译：编织与视觉颜色变化
公开(公告)号：US07575027B2
公开(公告)日：2009-08-18
申请号：US11649904
申请日：2007-01-05
申请人： Min-San Huang
发明人： Min-San Huang
IPC分类号： D03D13/00 , D03D25/00
CPC分类号： D03D13/00 , D03D13/004 , D03D15/00 , D03D15/0033 , D10B2501/00
摘要： A weave with a visual color variation, is interlaced by a plurality of longitudinal yarns and a plurality of latitudinal yarns. One of the longitudinal yarns and latitudinal yarns includes at least one protruding yarn and two color yarns with different colors. The protruding yarn has a plurality of protruding portions presenting on the surface of the weave. The two color yarns are arranged beside the protruding yarn respectively, and the two color yarns have a plurality of color portions presenting on the surface of the weave respectively. If the weave is observed from different viewing angles, the color portions are interfered by the protruding portion to make the weave show various visual color variations.
摘要翻译：具有视觉颜色变化的织物由多根纵向纱线和多根纬纱纱线交错。纵向纱线和纬纱中的一个包括至少一根突出纱线和两种颜色不同的彩色纱线。突出纱线具有在织物的表面上呈现的多个突出部分。双色纱线分别布置在突出纱线旁边，两根纱线分别在织物的表面上具有多个颜色部分。如果从不同的视角观察织物，则颜色部分被突出部分干扰，使织物显示各种视觉色彩变化。

4. 发明申请

US20080163952A1 Weave with visual color variation 有权
标题翻译：编织与视觉颜色变化
公开(公告)号：US20080163952A1
公开(公告)日：2008-07-10
申请号：US11649904
申请日：2007-01-05
申请人： Min-San Huang
发明人： Min-San Huang
IPC分类号： D03D49/00
CPC分类号： D03D13/00 , D03D13/004 , D03D15/00 , D03D15/0033 , D10B2501/00
摘要： The present invention relates to a weave with a visual color variation, which is interlaced by a plurality of longitudinal yarns and a plurality of latitudinal yarns. One of the longitudinal yarns and latitudinal yarns includes at least one protruding yarn and two color yarns with different colors. The protruding yarn has a plurality of protruding portions presenting on the surface of the weave. The two color yarns are arranged beside the protruding yarn respectively, and the two color yarns have a plurality of color portions presenting on the surface of the weave respectively. If the weave is observed from different viewing angles, the color portions are interfered by the protruding portion to make the weave show various visual color variations.
摘要翻译：本发明涉及一种具有视觉色彩变化的织物，其由多根纵向纱线和多根纬纱纱线交错。纵向纱线和纬纱中的一个包括至少一根突出纱线和两种颜色不同的彩色纱线。突出纱线具有在织物的表面上呈现的多个突出部分。双色纱线分别布置在突出纱线旁边，两根纱线分别在织物的表面上具有多个颜色部分。如果从不同的视角观察织物，则颜色部分被突出部分干扰，使织物显示各种视觉色彩变化。

5. 发明申请

US20070202300A1 Patterns having variable colors 审中-公开
标题翻译：具有可变颜色的图案
公开(公告)号：US20070202300A1
公开(公告)日：2007-08-30
申请号：US11507447
申请日：2006-08-22
申请人： Min-San Huang
发明人： Min-San Huang
IPC分类号： E01F9/04
CPC分类号： D06Q1/10 , A41D27/08 , Y10T428/24355 , Y10T428/24372
摘要： A pattern having variable colors can be attached on a soft material of wearing apparels or household cloths. The pattern is constituted of decorative blocks provided on the surface of the cloth or the soft material and a layer of transparent film covering on the decorative blocks. The surface of the transparent film is formed with refractive ripples thereon, so that the decorative blocks represent a visual effect of variable colors by means of refraction when viewed from different angles.
摘要翻译：具有可变颜色的图案可以附着在佩戴服装或家用布的柔软材料上。该图案由设置在布或软质材料的表面上的装饰块和覆盖在装饰块上的透明薄膜层构成。透明膜的表面在其上形成有折射波纹，使得当从不同角度观察时，装饰块通过折射来表示可变颜色的视觉效果。

6. 发明申请

US20070202299A1 Patterns having variable colors 有权
标题翻译：具有可变颜色的图案
公开(公告)号：US20070202299A1
公开(公告)日：2007-08-30
申请号：US11506813
申请日：2006-08-21
申请人： Min-San Huang
发明人： Min-San Huang
IPC分类号： E01F9/04
CPC分类号： D06Q1/10 , A41D27/08 , Y10T428/24 , Y10T428/24174 , Y10T428/24355 , Y10T428/24372 , Y10T428/24479 , Y10T428/24521 , Y10T428/24736
摘要： A pattern having variable colors can be attached on a soft material of wearing apparels or household cloths. The pattern is constituted of decorative blocks provided on the surface of the cloth or the soft material and a plurality of color-shielding pieces embedded on the surface of the decorative blocks. At least two opposite outer sides of the color-shielding piece are respectively provided with a colored block, so that the decorative blocks represent a visual effect of variable colors when viewed from different angles since the color-shielding pieces shield the colored blocks.
摘要翻译：具有可变颜色的图案可以附着在佩戴服装或家用布的柔软材料上。图案由设置在布或软质材料的表面上的装饰块和嵌入装饰块表面的多个彩色屏蔽片构成。彩色屏蔽片的至少两个相对的外侧分别设置有彩色块，使得当从不同的角度观察时，装饰块表示可变颜色的视觉效果，因为彩色屏蔽片屏蔽着色块。

7. 发明申请

US20060189074A1 STRUCTURE CONTAINING SELF-ALIGNED CONDUCTIVE LINES AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：包含自对准导线的结构及其制造方法
公开(公告)号：US20060189074A1
公开(公告)日：2006-08-24
申请号：US11162077
申请日：2005-08-29
申请人： Hann-Jye Hsu , Su-Yuan Chang , Min-San Huang
发明人： Hann-Jye Hsu , Su-Yuan Chang , Min-San Huang
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/115 , H01L27/11556
摘要： A method for fabricating self-aligned conductive lines is provided. A substrate with a plurality of isolation structures is provided. The isolation structures are protrusive from the surface of the substrate, and an active region is defined between two adjacent isolation structures. A plurality of semiconductor devices is formed in the active region. A conductive material layer is then formed on the substrate. Thereafter, a portion of the conductive material layer is removed by using the isolation structures as a removing-stop layer until the surfaces of the isolation structures are exposed and a plurality of conductive lines are formed in a self-aligned manner to electrically connect devices. As the size of the devices is scaled down, the design rule of the lithography process does not limit the size of self-aligned conductive lines. Consequently, the fabricated conductive lines are capable of effectively connecting the semiconductor devices.
摘要翻译：提供一种制造自对准导电线的方法。提供具有多个隔离结构的基板。隔离结构从衬底的表面突出，并且在两个相邻隔离结构之间限定有源区。在有源区域中形成多个半导体器件。然后在衬底上形成导电材料层。此后，通过使用隔离结构作为去除阻挡层去除导电材料层的一部分，直到隔离结构的表面露出，并且以自对准的方式形成多个导电线以电连接器件。随着器件的尺寸缩小，光刻工艺的设计规则并不限制自对准导电线的尺寸。因此，制造的导线能够有效地连接半导体器件。

8. 发明授权

US06913974B2 Flash memory device structure and manufacturing method thereof 有权
标题翻译：闪存器件结构及其制造方法
公开(公告)号：US06913974B2
公开(公告)日：2005-07-05
申请号：US10709590
申请日：2004-05-17
申请人： Chih-Wei Hung , Min-San Huang
发明人： Chih-Wei Hung , Min-San Huang
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L21/336 , H01L21/3205 , H01L21/8238
CPC分类号： H01L27/11556 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A flash memory device structure is provided. The flash memory device consists of a P-type substrate with an opening, a deep N-well region in the P-type substrate, a first gate structure and a second gate structure on the respective sidewalls of the opening, an insulating layer in the space between the first gate structure and the second gate structure, a source region in the P-type substrate at the bottom section of the opening, a drain region in the P-type substrate at the top section of the opening, a P-well region in the deep N-well region such that the junction between the P-well and the deep N-well region is at a level higher than the bottom section of the opening and a P-type pocket doping region in the P-type substrate on the sidewalls of the opening such that the P-type pocket doping region connects the P-well region with the source region.
摘要翻译：提供闪速存储器件结构。闪存器件由具有开口的P型衬底，P型衬底中的深N阱区域，在开口的相应侧壁上的第一栅极结构和第二栅极结构组成，其中绝缘层第一栅极结构和第二栅极结构之间的间隔，开口底部的P型衬底中的源极区域，开口顶部的P型衬底中的漏极区域，P阱区域，使得P阱和深N阱区域之间的接合点处于比开口的底部部分高的水平面，并且P型衬底中的P型口袋掺杂区域在开口的侧壁上，使得P型袋掺杂区域将P阱区域与源极区域连接。

9. 发明申请

US20050087892A1 [NAND FLASH MEMORY CELL ROW, NAND FLASH MEMORY CELL ARRAY, OPERATION AND FABRICATION METHOD THEREOF] 审中-公开
标题翻译： [NAND FLASH MEMORY CELL ROW，NAND FLASH MEMORY CELL ARRAY，OPERATION AND FABRICATION METHOD YOUEROF]
公开(公告)号：US20050087892A1
公开(公告)日：2005-04-28
申请号：US10709125
申请日：2004-04-15
申请人： Cheng-Yuan Hsu , Chih-Wei Hung , Da Sung , Min-San Huang
发明人： Cheng-Yuan Hsu , Chih-Wei Hung , Da Sung , Min-San Huang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115
摘要： A NAND flash memory cell array including a plurality of memory cell row is provided. Each of memory cell row includes a plurality of memory cells disposed between first selecting transistor and second selecting transistor connected in series. Each memory cell has a tunneling dielectric layer, a floating gate, an inter-gate dielectric, a control gate and source/drain regions. An erase gate is disposed between two adjacent memory cells. A plurality of word lines serve to connect the memory cells in rows. A source line serves to connect the source region of the first transistor in a row, whereas a plurality of bit lines serve to connect the drain region of second transistor in a row. A first selecting gate line and a second selecting gate line serve to connect the gate of the first transistor in a row and the gate of second transistor in a row respectively. A plurality of erase gate lines is connected to the erase gates in a row.
摘要翻译：提供包括多个存储单元行的NAND快闪存储单元阵列。每个存储单元行包括设置在串联连接的第一选择晶体管和第二选择晶体管之间的多个存储单元。每个存储单元具有隧道介电层，浮栅，栅极间电介质，控制栅极和源/漏区。擦除栅极设置在两个相邻的存储单元之间。多个字线用于以行的形式连接存储器单元。源极线用于将第一晶体管的源极区域连接成一行，而多个位线用于将第二晶体管的漏极区域连接成一行。第一选择栅极线和第二选择栅极线用于分别连接一行中的第一晶体管的栅极和第二晶体管的栅极。多条擦除栅极线一行连接到擦除栅极。

10. 发明授权

US06770934B1 Flash memory device structure and manufacturing method thereof 有权
标题翻译：闪存器件结构及其制造方法
公开(公告)号：US06770934B1
公开(公告)日：2004-08-03
申请号：US10249362
申请日：2003-04-03
申请人： Chih-Wei Hung , Min-San Huang
发明人： Chih-Wei Hung , Min-San Huang
IPC分类号： H01L29788
CPC分类号： H01L27/11556 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A flash memory device structure is provided. The flash memory device consists of a P-type substrate with an opening, a deep N-well region in the P-type substrate, a first gate structure and a second gate structure on the respective sidewalls of the opening, an insulating layer in the space between the first gate structure and the second gate structure, a source region in the P-type substrate at the bottom section of the opening, a drain region in the P-type substrate at the top section of the opening, a P-well region in the deep N-well region such that the junction between the P-well and the deep N-well region is at a level higher than the bottom section of the opening and a P-type pocket doping region in the P-type substrate on the sidewalls of the opening such that the P-type pocket doping region connects the P-well region with the source region.
摘要翻译：提供闪速存储器件结构。闪存器件由具有开口的P型衬底，P型衬底中的深N阱区域，在开口的相应侧壁上的第一栅极结构和第二栅极结构组成，其中绝缘层第一栅极结构和第二栅极结构之间的间隔，开口底部的P型衬底中的源极区域，开口顶部的P型衬底中的漏极区域，P阱区域，使得P阱和深N阱区域之间的接合点处于比开口的底部部分高的水平面，并且P型衬底中的P型口袋掺杂区域在开口的侧壁上，使得P型袋掺杂区域将P阱区域与源极区域连接。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式