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1. 发明申请

US20080132017A1 MANUFACTURING METHOD OF NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的制造方法
公开(公告)号：US20080132017A1
公开(公告)日：2008-06-05
申请号：US12014095
申请日：2008-01-15
申请人： Pin-Yao Wang , Liang-Chuan Lai
发明人： Pin-Yao Wang , Liang-Chuan Lai
IPC分类号： H01L21/336
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L29/40114 , H01L29/42328 , H01L29/66825
摘要： A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface of the floating gates is higher than that of the select gate forming a hollow structure on the select gate between the two floating gates. The control gate disposed on the substrate covers the select gate and the two floating gates and fills the hollow structure. The doped region is disposed in the substrate on one side of the two floating gates opposite to the select gate.
摘要翻译：描述了包括衬底，选择栅极，两个浮置栅极，控制栅极和掺杂区域的非易失性存储器。选择栅极设置在基板上。两个浮置栅极设置在选择栅极的两侧，并且浮栅的顶表面高于在两个浮置栅极之间的选择栅极上形成中空结构的选择栅极的顶表面。设置在基板上的控制栅覆盖选择栅极和两个浮动栅极并填充中空结构。掺杂区域设置在与选择栅极相对的两个浮动栅极的一侧上的衬底中。

2. 发明授权

US07235444B1 Method of fabricating non-volatile memory structure 失效
标题翻译：制造非易失性存储器结构的方法
公开(公告)号：US07235444B1
公开(公告)日：2007-06-26
申请号：US11620724
申请日：2007-01-07
申请人： Liang-Chuan Lai , Pin-Yao Wang
发明人： Liang-Chuan Lai , Pin-Yao Wang
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11526 , H01L27/11529
摘要： A substrate having a first dielectric layer, a first conductive layer and a second dielectric layer thereon is provided. A part of the second dielectric layer is removed to form a first opening having both ends with a select gate region respectively. The select gate region is constituted by a region with the second dielectric layer and a region without the second dielectric layer. A second conductive layer is formed to cover the second dielectric layer. A cap layer is formed on the second conductive layer. The cap layer, the second conductive layer, the second dielectric layer and the first conductive layer are patterned to form gate structures. The cap layer, the second conductive layer, the second dielectric layer and the first conductive layer between two adjacent select gate regions are removed to form a select gate structure. A doped region is formed in the substrate.
摘要翻译：提供了具有第一介电层，第一导电层和第二介电层的基板。去除第二电介质层的一部分以形成分别具有选择栅极区域的两端的第一开口。选择栅极区域由具有第二电介质层的区域和没有第二电介质层的区域构成。形成第二导电层以覆盖第二介电层。在第二导电层上形成盖层。将盖层，第二导电层，第二介电层和第一导电层图案化以形成栅极结构。除去两个相邻的选择栅区之间的覆盖层，第二导电层，第二介电层和第一导电层，以形成选择栅结构。在衬底中形成掺杂区域。

3. 发明申请

US20070001257A1 ANTI-PUNCH-THROUGH SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：抗穿透式半导体器件及其制造方法
公开(公告)号：US20070001257A1
公开(公告)日：2007-01-04
申请号：US11164825
申请日：2005-12-07
申请人： Liang-Chuan Lai , Pin-Yao Wang
发明人： Liang-Chuan Lai , Pin-Yao Wang
IPC分类号： H01L29/00
CPC分类号： H01L27/115 , H01L27/11521
摘要： An anti-punch-through semiconductor device is provided. The anti-punch-through semiconductor device includes a substrate, at least an isolation region and a plurality of trench devices. The trench device is disposed in the substrate. The trench device includes a source/drain region. The source/drain region of the trench device is disposed at the bottom of the trench device. The isolation region is disposed in the substrate and between the source/drain regions of each trench device.
摘要翻译：提供一种抗穿通半导体器件。抗穿通半导体器件包括至少隔离区域和多个沟槽器件的衬底。沟槽装置设置在基板中。沟槽器件包括源极/漏极区域。沟槽器件的源极/漏极区域设置在沟槽器件的底部。隔离区域设置在衬底中并且在每个沟槽器件的源极/漏极区域之间。

4. 发明申请

US20060211204A1 NON-VOLATILE MEMORY AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20060211204A1
公开(公告)日：2006-09-21
申请号：US11163858
申请日：2005-11-01
申请人： Min-San Huang , Dah-Chuan Chen , Liang-Chuan Lai
发明人： Min-San Huang , Dah-Chuan Chen , Liang-Chuan Lai
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L29/40114 , H01L29/66825
摘要： A method for fabricating a non-volatile memory is disclosed. First, a semiconductor device is formed in a substrate, and the top of the semiconductor device is higher than the surface of the substrate. Then, a first dielectric layer is formed on the substrate, and the first dielectric layer covers the semiconductor device and the substrate. A portion of the first dielectric layer is removed so as to retain a portion of the first dielectric layer on the sidewall of the semiconductor device and the substrate. Afterwards, a second dielectric layer and a conductive layer are sequentially formed on the substrate, and a corresponding pair of mask spacers is formed on the conductive layer disposed on the sidewall of the semiconductor device. Finally, the mask spacers are used as an etching mask to continuously etch a portion of the conductive layer until the surface of the second dielectric layer is exposed.
摘要翻译：公开了一种用于制造非易失性存储器的方法。首先，在衬底中形成半导体器件，并且半导体器件的顶部高于衬底的表面。然后，在基板上形成第一电介质层，第一电介质层覆盖半导体器件和基板。去除第一电介质层的一部分，以便将第一电介质层的一部分保持在半导体器件和衬底的侧壁上。之后，在衬底上依次形成第二电介质层和导电层，并且在设置在半导体器件的侧壁上的导电层上形成相应的一对掩模间隔物。最后，将掩模间隔物用作蚀刻掩模，以连续蚀刻导电层的一部分，直到第二介电层的表面露出。

5. 发明授权

US08268562B2 Biomarkers for predicting response of esophageal cancer patient to chemoradiotherapy 有权
标题翻译：用于预测食管癌患者对放化疗的反应的生物标志物
公开(公告)号：US08268562B2
公开(公告)日：2012-09-18
申请号：US12582357
申请日：2009-10-20
申请人： Pei-Chun Chen , Yen-Ching Chen , Liang-Chuan Lai , Mong-Hsun Tsai , Shin-Kuang Chen , Pei-Wen Yang , Jang-Ming Lee , Eric Y. Chuang , Chuhsing K. Hsiao
发明人： Pei-Chun Chen , Yen-Ching Chen , Liang-Chuan Lai , Mong-Hsun Tsai , Shin-Kuang Chen , Pei-Wen Yang , Jang-Ming Lee , Eric Y. Chuang , Chuhsing K. Hsiao
IPC分类号： C12Q1/68 , C07H21/04 , C12P19/34
CPC分类号： C12Q1/6886 , C12Q2600/106 , C12Q2600/156
摘要： The present invention relates to novel genetic markers associated with response of a patient with esophageal cancer (ECa) to chemoradiation therapy, and particularly to methods and kits for predicting an ECa patient's response to chemoradiation therapy by genotyping of the markers.
摘要翻译：本发明涉及与食管癌患者（ECa）对化学放疗疗法的反应相关的新型遗传标记，特别涉及用于通过标记基因分型来预测ECa患者对放化疗放疗反应的方法和试剂盒。

6. 发明申请

US20110091871A1 BIOMARKERS FOR PREDICTING RESPONSE OF ESOPHAGEAL CANCER PATIENT TO CHEMORADIOTHERAPY 有权
标题翻译：预防食管癌患者对化疗的反应的生物标志物
公开(公告)号：US20110091871A1
公开(公告)日：2011-04-21
申请号：US12582357
申请日：2009-10-20
申请人： Pei-Chun Chen , Yen-Ching Chen , Liang-Chuan Lai , Mong-Hsun Tsai , Shin-Kuang Chen , Pei-Wen Yang , Jang-Ming Lee , Eric Y. Chuang , Chuhsing K. Hsiao
发明人： Pei-Chun Chen , Yen-Ching Chen , Liang-Chuan Lai , Mong-Hsun Tsai , Shin-Kuang Chen , Pei-Wen Yang , Jang-Ming Lee , Eric Y. Chuang , Chuhsing K. Hsiao
IPC分类号： C12Q1/68
CPC分类号： C12Q1/6886 , C12Q2600/106 , C12Q2600/156
摘要： The present invention relates to novel genetic markers associated with response of a patient with esophageal cancer (ECa) to chemoradiation therapy, and particularly to methods and kits for predicting an ECa patient's response to chemoradiation therapy by genotyping of the markers.
摘要翻译：本发明涉及与食管癌患者（ECa）对化学放疗疗法的反应相关的新型遗传标记，特别涉及用于通过标记基因分型来预测ECa患者对放化疗放疗反应的方法和试剂盒。

7. 发明申请

US20090026525A1 MEMORY AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：用于制造它的记忆和方法
公开(公告)号：US20090026525A1
公开(公告)日：2009-01-29
申请号：US11872723
申请日：2007-10-16
申请人： Pin-Yao Wang , Liang-Chuan Lai , Michael Ying-li Liu
发明人： Pin-Yao Wang , Liang-Chuan Lai , Michael Ying-li Liu
IPC分类号： H01L29/788 , H01L21/44
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： A method for fabricating a memory is provided. A tunneling dielectric layer, a first conductive layer, and a mask layer are formed on a substrate. The mask layer, the first conductive layer, the tunneling dielectric layer, and the substrate are patterned to form trenches in the substrate. A passivation layer and isolation structures are formed in sequence to fill the trenches, and the etching rate of the isolation structures is greater than that of the passivation layer. After the mask layer is removed, a second conductive layer is formed on the first conductive layer. Portions of the isolation structures are removed to expose the sidewalls of the first and the second conductive layers. Further, a third conductive layer is formed on the exposed sidewalls of the first and the second conductive layers. An inter-gate dielectric layer and a control gate are formed on the substrate.
摘要翻译：提供了一种用于制造存储器的方法。在衬底上形成隧道电介质层，第一导电层和掩模层。图案化掩模层，第一导电层，隧道电介质层和衬底，以在衬底中形成沟槽。顺序地形成钝化层和隔离结构以填充沟槽，并且隔离结构的蚀刻速率大于钝化层的蚀刻速率。在去除掩模层之后，在第一导电层上形成第二导电层。去除部分隔离结构以露出第一和第二导电层的侧壁。此外，第三导电层形成在第一和第二导电层的暴露的侧壁上。栅极间介质层和控制栅极形成在衬底上。

8. 发明授权

US07183607B1 Non-volatile memory structure 失效
标题翻译：非易失性存储器结构
公开(公告)号：US07183607B1
公开(公告)日：2007-02-27
申请号：US11308621
申请日：2006-04-13
申请人： Liang-Chuan Lai , Pin-Yao Wang
发明人： Liang-Chuan Lai , Pin-Yao Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory structure including a substrate, a first memory cell row, a first source/drain region, and a second source/drain region is described. The first memory cell row is disposed on the substrate and includes a plurality of memory cells, two select gate structures, and a plurality of doped regions. The select gate structures are respectively disposed on the substrate at one side of the outmost memory cell among the memory cells, and the select gates have a tapered corner at one side far from the memory cells. The doped regions are respectively disposed in the substrate between two memory cells as well as in the substrate between the memory cells and the select gate structures. The first and the second source/drain regions are respectively disposed in the substrate at both sides of the first memory cell row.
摘要翻译：描述了包括衬底，第一存储单元行，第一源极/漏极区域和第二源极/漏极区域的非易失性存储器结构。第一存储单元行设置在基板上，并且包括多个存储单元，两个选择栅极结构和多个掺杂区域。选择栅极结构分别设置在存储单元中最外层存储单元的一侧的衬底上，并且选择栅极在远离存储单元的一侧具有锥形角。掺杂区域分别设置在两个存储单元之间的衬底中以及存储单元和选择栅极结构之间的衬底中。第一和第二源极/漏极区域分别设置在第一存储单元行的两侧的衬底中。

9. 发明申请

US20060291281A1 NON-VOLATILE MEMORY, MANUFACTURING AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器，其制造和操作方法
公开(公告)号：US20060291281A1
公开(公告)日：2006-12-28
申请号：US11164969
申请日：2005-12-13
申请人： Pin-Yao Wang , Liang-Chuan Lai
发明人： Pin-Yao Wang , Liang-Chuan Lai
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0458 , G11C16/0475 , H01L27/11521 , H01L27/11568
摘要： A non-volatile memory having a substrate, a select gate, a pair of charge storage layers, a pair of source/drain regions and a control gate is provided. At least a pair of trenches are formed in the substrate. The select gate is formed on the substrate between the pair of trenches. A pair of charge storage layers is formed on the sidewalls of the trenches next to the select gate. A pair of source/drain regions is formed in the substrate at the bottom of the trenches. The control gate is formed on the substrate to fill the trenches completely.
摘要翻译：提供具有基板，选择栅极，一对电荷存储层，一对源极/漏极区域和控制栅极的非易失性存储器。在衬底中形成至少一对沟槽。选择栅极形成在一对沟槽之间的衬底上。在选择栅极旁边的沟槽的侧壁上形成一对电荷存储层。在沟槽底部的衬底中形成一对源极/漏极区域。控制栅极形成在基板上以完全填充沟槽。

10. 发明申请

US20130017961A1 Biomarkers for predicting response of esophageal cancer patient to chemoradiotherapy 审中-公开
标题翻译：用于预测食管癌患者对放化疗的反应的生物标志物
公开(公告)号：US20130017961A1
公开(公告)日：2013-01-17
申请号：US13584610
申请日：2012-08-13
申请人： Pei-Chun Chen , Yen-Ching Chen , Liang-Chuan Lai , Mong-Hsun Tsai , Shin-Kuang Chen , Pei-Wen Yang , Jang-Ming Lee , Eric Y. Chuang , Chuhsing K. Hsiao
发明人： Pei-Chun Chen , Yen-Ching Chen , Liang-Chuan Lai , Mong-Hsun Tsai , Shin-Kuang Chen , Pei-Wen Yang , Jang-Ming Lee , Eric Y. Chuang , Chuhsing K. Hsiao
IPC分类号： C40B20/08
CPC分类号： C12Q1/6886 , C12Q2600/106 , C12Q2600/156
摘要： The present invention relates to novel genetic markers associated with response of a patient with esophageal cancer (ECa) to chemoradiation therapy, and particularly to methods and kits for predicting an ECa patient's response to chemoradiation therapy by genotyping of the markers.
摘要翻译：本发明涉及与食管癌患者（ECa）对化学放疗疗法的反应相关的新型遗传标记，特别涉及用于通过标记基因分型来预测ECa患者对放化疗放疗反应的方法和试剂盒。

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