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1. 发明授权

US07042776B2 Method and circuit for dynamic read margin control of a memory array 失效
标题翻译：存储器阵列的动态读取余量控制的方法和电路
公开(公告)号：US07042776B2
公开(公告)日：2006-05-09
申请号：US10708236
申请日：2004-02-18
申请人： Miles G. Canada , Stephen F. Geissler , Robert M. Houle , Dongho Lee , Vinod Ramadurai , Mathew I. Ringler , Gerard M. Salem , Timothy J. Vonreyn
发明人： Miles G. Canada , Stephen F. Geissler , Robert M. Houle , Dongho Lee , Vinod Ramadurai , Mathew I. Ringler , Gerard M. Salem , Timothy J. Vonreyn
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/1045 , G11C2207/065 , G11C2207/2254
摘要： A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.
摘要翻译：一种用于调整自定时存储器阵列的读取余量的方法和电路。该电子电路包括：存储单元阵列，包括适于设置存储单元阵列的基本读时间延迟的读出放大器自定时解码电路; 以及耦合到所述存储单元阵列的读延迟调整电路，所述读延迟调整电路适于基于所述存储单元阵列的工作频率来调整所述存储器阵列的基本读时间延迟。

2. 发明授权

US07480810B2 Voltage droop dynamic recovery 失效
标题翻译：电压下垂动态恢复
公开(公告)号：US07480810B2
公开(公告)日：2009-01-20
申请号：US11276101
申请日：2006-02-14
申请人： Christopher J. Gonzalez , Paul D. Kartschoke , Vinod Ramadurai , Mathew I. Ringler
发明人： Christopher J. Gonzalez , Paul D. Kartschoke , Vinod Ramadurai , Mathew I. Ringler
IPC分类号： G06F1/00 , G06F11/30
CPC分类号： G06F1/28
摘要： Method and systems for dynamically recovering from voltage droops are disclosed. In one embodiment, a microprocessor coupled to a plurality of voltage sensing circuits is provided. The microprocessor includes an instruction sequencing unit and pipeline including a first series of instructions. A central voltage droop detection processor may be coupled to each of the voltage sensing circuits and the microprocessor. Voltage droop is detected using a voltage sensing circuit, after which processing of the microprocessor is interrupted. The pipeline may then be cleared. Subsequently, a second series of instructions including the first series of instructions, and additional instructions are issued. The additional instructions may include stall instructions that cause a delay in processing of the first series of instructions, which prevents re-occurrence of the voltage droop. The interruption and re-issuing also signals the microprocessor that all the data in a particular instruction stream might not be valid and allows recovery.
摘要翻译：公开了用于从电压下降动态恢复的方法和系统。在一个实施例中，提供耦合到多个电压感测电路的微处理器。微处理器包括指令排序单元和包括第一系列指令的流水线。中央电压下降检测处理器可以耦合到每个电压感测电路和微处理器。使用电压检测电路检测电压下降，之后中断微处理器的处理。然后可以清除管道。随后，发出包括第一系列指令和附加指令的第二系列指令。附加指令可以包括导致处理第一系列指令的延迟的停止指令，这防止电压下降的再次发生。中断和重新发出也向微处理器指示特定指令流中的所有数据可能无效并允许恢复。

3. 发明申请

US20050180228A1 METHOD AND CIRCUIT FOR DYNAMIC READ MARGIN CONTROL OF A MEMORY ARRAY 失效
标题翻译：用于动态读取记忆阵列控制的方法和电路
公开(公告)号：US20050180228A1
公开(公告)日：2005-08-18
申请号：US10708236
申请日：2004-02-18
申请人： Miles Canada , Stephen Geissler , Robert Houle , Dongho Lee , Vinod Ramadurai , Mathew Ringler , Gerard Salem , Timothy Vonreyn
发明人： Miles Canada , Stephen Geissler , Robert Houle , Dongho Lee , Vinod Ramadurai , Mathew Ringler , Gerard Salem , Timothy Vonreyn
IPC分类号： G11C7/00 , G11C7/08 , G11C7/10
CPC分类号： G11C7/08 , G11C7/1045 , G11C2207/065 , G11C2207/2254
摘要： A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.
摘要翻译：一种用于调整自定时存储器阵列的读取余量的方法和电路。该电子电路包括：存储单元阵列，包括适于设置存储单元阵列的基本读时间延迟的读出放大器自定时解码电路; 以及耦合到所述存储单元阵列的读延迟调整电路，所述读延迟调整电路适于基于所述存储单元阵列的工作频率来调整所述存储器阵列的基本读时间延迟。

4. 发明授权

US08279687B2 Single supply sub VDD bit-line precharge SRAM and method for level shifting 有权
标题翻译：单电源VDD位线预充电SRAM和电平转换方法
公开(公告)号：US08279687B2
公开(公告)日：2012-10-02
申请号：US12779608
申请日：2010-05-13
申请人： Chad A. Adams , George M. Braceras , Daniel M Nelson , Harold Pilo , Vinod Ramadurai
发明人： Chad A. Adams , George M. Braceras , Daniel M Nelson , Harold Pilo , Vinod Ramadurai
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/04 , G11C11/419
摘要： A reduced bitline precharge level has been found to increase the SRAM Beta ratio, thus improving the stability margin. The precharge level is also supplied to Sense amplifier, write driver, and source voltages for control signals. In the sense amplifier, the lower precharge voltage compensates for performance loss in the bit-cell by operating global data-line drivers with increased overdrive. In the write driver, the reduced voltage improves the Bitline discharge rate, improves the efficiency of the negative boost write assist, and decreases the reliability exposure of transistors in the write path from negative boost circuit.
摘要翻译：已经发现降低的位线预充电水平增加了SRAM Beta比率，从而提高了稳定裕度。预充电电平也提供给Sense放大器，写入驱动器和源电压用于控制信号。在读出放大器中，较低的预充电电压通过以增加的超速驱动来操作全局数据线驱动器来补偿位单元中的性能损失。在写入驱动器中，降低的电压提高了位线放电速率，提高了负升压写入辅助的效率，并降低了来自负升压电路的写入通路中的晶体管的可靠性暴露。

5. 发明授权

US07791977B2 Design structure for low overhead switched header power savings apparatus 失效
标题翻译：低开销交换机头节能设备的设计结构
公开(公告)号：US07791977B2
公开(公告)日：2010-09-07
申请号：US12116322
申请日：2008-05-07
申请人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
发明人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C5/147 , G11C5/148 , G11C8/12
摘要： A design structure embodied in a machine readable medium used in a design process includes a tri-state power gating apparatus for reducing leakage current in a memory array. The apparatus includes a first distributed header device coupled to the memory array, the first distributed header device is configured for limiting leakage current through the memory array; and a header driver operatively coupled to the first distributed header device for enabling tri-state operation of the first distributed header device, wherein tri-state operation includes sleep mode, wake mode, and retention mode.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构包括用于减少存储器阵列中的漏电流的三态电源门控装置。所述装置包括耦合到所述存储器阵列的第一分配报头装置，所述第一分配报头装置被配置为限制通过所述存储器阵列的泄漏电流; 以及头部驱动器，其可操作地耦合到所述第一分配报头装置，用于实现所述第一分配报头装置的三态操作，其中三态操作包括睡眠模式，唤醒模式和保持模式。

6. 发明授权

US07788443B2 Transparent multi-hit correction in associative memories 有权
标题翻译：联想记忆中的透明多点校正
公开(公告)号：US07788443B2
公开(公告)日：2010-08-31
申请号：US11609416
申请日：2006-12-12
申请人： Michael J. Lee , Vinod Ramadurai , Bao G. Truong
发明人： Michael J. Lee , Vinod Ramadurai , Bao G. Truong
IPC分类号： G06F13/00 , G06F13/28 , G06F11/00 , G11C15/00
CPC分类号： G11C15/04 , G06F12/1027
摘要： A mechanism is provided for transparent multi-hit correction in associative memories. A content associative memory (CAM) device is provided that transparently and independently executes a precise corrective action in the case of a multiple hit being detected. The wordlines of a CAM array are modified to include a valid bit storage circuit element that indicates whether or not the corresponding wordline is valid or not. In operation, if multiple hits are detected, the multiple hit is signaled to the host system and the particular entries in the CAM array corresponding to the multiple hits are invalidated by setting their associated valid bit storage circuit elements to an invalid value or clearing the value in the associated valid bit storage circuit element. Any data returned to the host system as a result of the multiple hits is invalidated in the host system in response to the signaling of the multiple hits.
摘要翻译：提供了一种用于联想记忆中的透明多点校正的机制。提供内容关联存储器（CAM）装置，其在检测到多重命中的情况下透明地且独立地执行精确的校正动作。 CAM阵列的字线被修改为包括有效位存储电路元件，其指示对应的字线是否有效。在操作中，如果检测到多个命中，则将多次命中信号发送到主机系统，并且通过将其相关联的有效位存储电路元件设置为无效值或清除该值来使与多次命中相对应的CAM阵列中的特定条目无效在相关联的有效位存储电路元件中。作为多次命中的结果返回到主机系统的任何数据在主机系统中响应于多次命中的信令而无效。

7. 发明授权

US07450413B2 Configurable SRAM system and method 有权
标题翻译：可配置的SRAM系统和方法
公开(公告)号：US07450413B2
公开(公告)日：2008-11-11
申请号：US11463917
申请日：2006-08-11
申请人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
发明人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译：静态随机存取存储器（SRAM）电路包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。

8. 发明申请

US20080273374A1 METHODS OF OPERATING AND DESIGNING MEMORY CIRCUITS HAVING SINGLE-ENDED MEMORY CELLS WITH IMPROVED READ STABILITY 失效
标题翻译：具有改进的读取稳定性的具有单端存储器单元的存储器电路的操作和设计方法
公开(公告)号：US20080273374A1
公开(公告)日：2008-11-06
申请号：US12174688
申请日：2008-07-17
申请人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
发明人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.
摘要翻译：用于与READ和WRITE字线以及READ和WRITE位线互连的存储单元包括逻辑存储元件，例如由第一反相器形成的触发器和与第一反相器交叉耦合的第二反相器。存储元件具有第一和第二端子以及被配置为与第一电源电压互连的存储元件电源电压端子。 WRITE访问设备被配置为在WRITE字线的控制下选择性地将第一终端与WRITE位线互连，并且一对串行READ访问设备被配置为当READ字线活动时将READ位线接地，并且第二终端处于高逻辑级。当将大于第一电源电压的第二电源电压施加到写字线时，基本上不使用互补的写位线，可以将逻辑“1”写入存储元件。

9. 发明授权

US07382165B2 Method for matching semiconductor device behavior 失效
标题翻译：匹配半导体器件行为的方法
公开(公告)号：US07382165B2
公开(公告)日：2008-06-03
申请号：US11466471
申请日：2006-08-23
申请人： Christopher Gonzalez , Vinod Ramadurai , Norman Jay Rohrer
发明人： Christopher Gonzalez , Vinod Ramadurai , Norman Jay Rohrer
IPC分类号： G01R23/02
CPC分类号： H03K19/177 , H03K17/002
摘要： A selection circuit and method. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.
摘要翻译：一种选择电路及方法。选择电路包括逻辑电路，子电路阵列和彼此电耦合的开关电路。选择电路经受第一操作条件。开关电路从阵列中选择一组子电路。选择电路产生第一频率。选择电路经受与第一操作条件不同的第二操作条件，并产生第二频率。将第一频率和第二频率之间的第一频率差与预定的频率差进行比较，以确定第一频率差是否大约等于预定的频率差。

10. 发明授权

US07602635B2 Structure for a configurable SRAM system and method 有权
标题翻译：可配置SRAM系统和方法的结构
公开(公告)号：US07602635B2
公开(公告)日：2009-10-13
申请号：US11947092
申请日：2007-11-29
申请人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
发明人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
IPC分类号： G11C11/00
CPC分类号： G11C11/4125 , G11C11/413
摘要： A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译：静态随机存取存储器（SRAM）电路的设计结构包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。

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