专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07042776B2 Method and circuit for dynamic read margin control of a memory array 失效
标题翻译：存储器阵列的动态读取余量控制的方法和电路
公开(公告)号：US07042776B2
公开(公告)日：2006-05-09
申请号：US10708236
申请日：2004-02-18
申请人： Miles G. Canada , Stephen F. Geissler , Robert M. Houle , Dongho Lee , Vinod Ramadurai , Mathew I. Ringler , Gerard M. Salem , Timothy J. Vonreyn
发明人： Miles G. Canada , Stephen F. Geissler , Robert M. Houle , Dongho Lee , Vinod Ramadurai , Mathew I. Ringler , Gerard M. Salem , Timothy J. Vonreyn
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/1045 , G11C2207/065 , G11C2207/2254
摘要： A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.
摘要翻译：一种用于调整自定时存储器阵列的读取余量的方法和电路。该电子电路包括：存储单元阵列，包括适于设置存储单元阵列的基本读时间延迟的读出放大器自定时解码电路; 以及耦合到所述存储单元阵列的读延迟调整电路，所述读延迟调整电路适于基于所述存储单元阵列的工作频率来调整所述存储器阵列的基本读时间延迟。

2. 发明授权

US07480810B2 Voltage droop dynamic recovery 失效
标题翻译：电压下垂动态恢复
公开(公告)号：US07480810B2
公开(公告)日：2009-01-20
申请号：US11276101
申请日：2006-02-14
申请人： Christopher J. Gonzalez , Paul D. Kartschoke , Vinod Ramadurai , Mathew I. Ringler
发明人： Christopher J. Gonzalez , Paul D. Kartschoke , Vinod Ramadurai , Mathew I. Ringler
IPC分类号： G06F1/00 , G06F11/30
CPC分类号： G06F1/28
摘要： Method and systems for dynamically recovering from voltage droops are disclosed. In one embodiment, a microprocessor coupled to a plurality of voltage sensing circuits is provided. The microprocessor includes an instruction sequencing unit and pipeline including a first series of instructions. A central voltage droop detection processor may be coupled to each of the voltage sensing circuits and the microprocessor. Voltage droop is detected using a voltage sensing circuit, after which processing of the microprocessor is interrupted. The pipeline may then be cleared. Subsequently, a second series of instructions including the first series of instructions, and additional instructions are issued. The additional instructions may include stall instructions that cause a delay in processing of the first series of instructions, which prevents re-occurrence of the voltage droop. The interruption and re-issuing also signals the microprocessor that all the data in a particular instruction stream might not be valid and allows recovery.
摘要翻译：公开了用于从电压下降动态恢复的方法和系统。在一个实施例中，提供耦合到多个电压感测电路的微处理器。微处理器包括指令排序单元和包括第一系列指令的流水线。中央电压下降检测处理器可以耦合到每个电压感测电路和微处理器。使用电压检测电路检测电压下降，之后中断微处理器的处理。然后可以清除管道。随后，发出包括第一系列指令和附加指令的第二系列指令。附加指令可以包括导致处理第一系列指令的延迟的停止指令，这防止电压下降的再次发生。中断和重新发出也向微处理器指示特定指令流中的所有数据可能无效并允许恢复。

3. 发明授权

US06989696B2 System and method for synchronizing divide-by counters 失效
标题翻译：用于同步分频计数器的系统和方法
公开(公告)号：US06989696B2
公开(公告)日：2006-01-24
申请号：US10707066
申请日：2003-11-19
申请人： Rolf Hilgendorf , Jens Kuenzer , Cédric Lichtenau , Thomas Pflueger , Mathew I. Ringler , Gerard M. Salem , Peter A. Sandon , Dana J. Thygesen , Ulrich Weiss
发明人： Rolf Hilgendorf , Jens Kuenzer , Cédric Lichtenau , Thomas Pflueger , Mathew I. Ringler , Gerard M. Salem , Peter A. Sandon , Dana J. Thygesen , Ulrich Weiss
IPC分类号： H03L7/00
CPC分类号： H03L7/06
摘要： A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.
摘要翻译：能够将多个处理器（A，B）的频率分频计数器（124A，124BB）同时复位的同步系统为零，而不管分频频率信号（Mclk / n信号（168A，168B）），并且与处理器中的Mclk / n信号经历的时钟网格延迟的大小无关。同步系统包括用于在未分割信号中模拟的每个处理器的网格延迟电路（176A，176BB）（Mclk / 1信号（136 < / SUB>，136 B））由该处理器中的Mclk / n信号经历的时钟网格延迟，以便提供Lclk信号（172 ，172 _{B ）。相位检测器检测Mclk / n信号和Sysclk信号之间的相位偏移（112），并将异步偏移信号（194A，192B）发送到计数器基于偏移信号将再分配计数器复位为零的重新设置器（196A，196BB）。}

4. 发明授权

US07106110B2 Clock dithering system and method during frequency scaling 有权
标题翻译：时钟抖动系统和方法在频率缩放期间
公开(公告)号：US07106110B2
公开(公告)日：2006-09-12
申请号：US10710681
申请日：2004-07-28
申请人： Miles G. Canada , Erwin B. Cohen , Jay G. Heaslip , Cedric Lichtenau , Thomas Pflueger , Mathew I. Ringler
发明人： Miles G. Canada , Erwin B. Cohen , Jay G. Heaslip , Cedric Lichtenau , Thomas Pflueger , Mathew I. Ringler
IPC分类号： H03B19/00
CPC分类号： G06F1/08 , G06F1/324 , Y02D10/126
摘要： A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for a predetermined number of cycles; and setting the clock frequency to the second frequency after the predetermined number of cycles.
摘要翻译：一种将集成电路装置的时钟频率从第一频率转换到第二频率的系统和方法，包括根据抖动模式在第一频率和第二频率之间交替，交替发生预定数量的周期; 并且在预定次数的周期之后将时钟频率设置为第二频率。

5. 发明申请

US20080195986A1 POWER GRID TUNING FOR DC VOLTAGE EQUALIZATION 审中-公开
标题翻译：用于直流电压均衡的电网调谐
公开(公告)号：US20080195986A1
公开(公告)日：2008-08-14
申请号：US11674325
申请日：2007-02-13
申请人： Erwin B. Cohen , Mathew I. Ringler
发明人： Erwin B. Cohen , Mathew I. Ringler
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： A method for tuning a plurality of supply voltages across and integrated circuit (IC) package that supplies a number of voltage supply regions within an IC chip. The inventive method includes extracting a power draw for each voltage supply region and the region's functional circuit blocks to generate a current map, assigning C4 bumps and module pins, and designing an IC package layout to define a supply grid of metal conductive power distribution wiring, analyzing the IC package layout using an IR-drop application, creating an internal plane voltage map and an internal plane current map for each of the IC package voltage supply planes and identifying required via and plane current changes necessary to tune the IC package in accordance with plane voltage and plane current maps, and repeating the steps of assigning, analyzing and creating until the IR drops within the voltage supply regions of the IC package are thoroughly balanced.
摘要翻译：一种用于调整多个电源电压的方法以及提供IC芯片内的多个电压供应区域的集成电路（IC）封装。本发明的方法包括提取每个电压供应区域和区域的功能电路块的功率消耗，以产生电流映射，分配C4凸块和模块引脚，以及设计IC封装布局以定义金属导电配电布线的电网，使用IR-drop应用分析IC封装布局，为每个IC封装电压供应平面创建一个内部平面电压图和一个内部平面电流映射，并根据以下要求识别所需的通过和平面电流变化，以调整IC封装平面电压和平面电流映射，并且重复分配，分析和创建的步骤，直到IC封装的电压供应区域内的IR下降被彻底平衡为止。

6. 发明授权

US07242237B2 Supply switch circuit for implementing a switchable on-chip high voltage supply 失效
标题翻译：用于实现可切换片上高压电源的开关电路
公开(公告)号：US07242237B2
公开(公告)日：2007-07-10
申请号：US10877239
申请日：2004-06-25
申请人： David Howard Allen , Lew Chua-Eoan , Mathew I. Ringler
发明人： David Howard Allen , Lew Chua-Eoan , Mathew I. Ringler
IPC分类号： H03K17/687
CPC分类号： H03K17/6871 , H03K17/102 , Y10T307/858
摘要： A supply switch circuit is provided for implementing a switchable on-chip high voltage supply. A stack of transistors is coupled between an on-chip high voltage supply and a circuit node. A control signal is coupled to the stack of transistors for selectively switching the high voltage supply to the circuit node. The control signal is coupled to a voltage divider included with the stack of transistors to limit a maximum node voltage within the stack of transistors.
摘要翻译：提供用于实现可切换片上高压电源的电源开关电路。晶体管堆叠耦合在片上高压电源和电路节点之间。控制信号耦合到晶体管堆，以选择性地将高压电源切换到电路节点。控制信号耦合到晶体管堆叠中包括的分压器，以限制晶体管堆叠内的最大节点电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式