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1. 发明申请

US20080273374A1 METHODS OF OPERATING AND DESIGNING MEMORY CIRCUITS HAVING SINGLE-ENDED MEMORY CELLS WITH IMPROVED READ STABILITY 失效
标题翻译：具有改进的读取稳定性的具有单端存储器单元的存储器电路的操作和设计方法
公开(公告)号：US20080273374A1
公开(公告)日：2008-11-06
申请号：US12174688
申请日：2008-07-17
申请人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
发明人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.
摘要翻译：用于与READ和WRITE字线以及READ和WRITE位线互连的存储单元包括逻辑存储元件，例如由第一反相器形成的触发器和与第一反相器交叉耦合的第二反相器。存储元件具有第一和第二端子以及被配置为与第一电源电压互连的存储元件电源电压端子。 WRITE访问设备被配置为在WRITE字线的控制下选择性地将第一终端与WRITE位线互连，并且一对串行READ访问设备被配置为当READ字线活动时将READ位线接地，并且第二终端处于高逻辑级。当将大于第一电源电压的第二电源电压施加到写字线时，基本上不使用互补的写位线，可以将逻辑“1”写入存储元件。

2. 发明申请

US20080276205A1 COMPUTER PROGRAM PRODUCT FOR DESIGNING MEMORY CIRCUITS HAVING SINGLE-ENDED MEMORY CELLS WITH IMPROVED READ STABILITY 有权
标题翻译：用于设计具有改进的读取稳定性的单端存储器单元的存储器电路的计算机程序产品
公开(公告)号：US20080276205A1
公开(公告)日：2008-11-06
申请号：US12174707
申请日：2008-07-17
申请人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
发明人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
IPC分类号： G06F17/50 , G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.
摘要翻译：用于与READ和WRITE字线以及READ和WRITE位线互连的存储单元包括逻辑存储元件，例如由第一反相器形成的触发器和与第一反相器交叉耦合的第二反相器。存储元件具有第一和第二端子以及被配置为与第一电源电压互连的存储元件电源电压端子。 WRITE访问设备被配置为在WRITE字线的控制下选择性地将第一终端与WRITE位线互连，并且一对串行READ访问设备被配置为当READ字线活动时将READ位线接地，并且第二终端处于高逻辑级。当将大于第一电源电压的第二电源电压施加到写字线时，基本上不使用互补的写位线，可以将逻辑“1”写入存储元件。

3. 发明申请

US20080192525A1 SINGLE-ENDED MEMORY CELL WITH IMPROVED READ STABILITY, MEMORY USING THE CELL, AND METHODS OF OPERATING AND DESIGNING SAME 有权
标题翻译：具有改进的读取稳定性的单端存储器单元，使用单元的存储器及其操作和设计方法
公开(公告)号：US20080192525A1
公开(公告)日：2008-08-14
申请号：US11674292
申请日：2007-02-13
申请人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
发明人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line
摘要翻译：用于与READ和WRITE字线以及READ和WRITE位线互连的存储单元包括逻辑存储元件，例如由第一反相器形成的触发器和与第一反相器交叉耦合的第二反相器。存储元件具有第一和第二端子以及被配置为与第一电源电压互连的存储元件电源电压端子。 WRITE访问设备被配置为在WRITE字线的控制下选择性地将第一终端与WRITE位线互连，并且一对串行READ访问设备被配置为当READ字线活动时将READ位线接地，并且第二终端处于高逻辑级。当将大于第一电源电压的第二电源电压施加到写字线时，基本上不使用互补的写位线，可以将逻辑“1”写入存储元件

4. 发明授权

US07733689B2 Methods of operating and designing memory circuits having single-ended memory cells with improved read stability 失效
标题翻译：具有改善的读稳定性的具有单端存储单元的存储电路的操作和设计方法
公开(公告)号：US07733689B2
公开(公告)日：2010-06-08
申请号：US12174688
申请日：2008-07-17
申请人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
发明人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
IPC分类号： G11C11/40
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.
摘要翻译：用于与READ和WRITE字线以及READ和WRITE位线互连的存储单元包括逻辑存储元件，例如由第一反相器形成的触发器和与第一反相器交叉耦合的第二反相器。存储元件具有第一和第二端子以及被配置为与第一电源电压互连的存储元件电源电压端子。 WRITE访问设备被配置为在WRITE字线的控制下选择性地将第一终端与WRITE位线互连，并且一对串行READ访问设备被配置为当READ字线活动时将READ位线接地，并且第二终端处于高逻辑级。当将大于第一电源电压的第二电源电压施加到写字线时，基本上不使用互补的写位线，可以将逻辑“1”写入存储元件。

5. 发明授权

US07890907B2 Computer program product for designing memory circuits having single-ended memory cells with improved read stability 有权
标题翻译：用于设计具有改善的读稳定性的单端存储单元的存储器电路的计算机程序产品
公开(公告)号：US07890907B2
公开(公告)日：2011-02-15
申请号：US12174707
申请日：2008-07-17
申请人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
发明人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
IPC分类号： G06F17/50
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.
摘要翻译：用于与READ和WRITE字线以及READ和WRITE位线互连的存储单元包括逻辑存储元件，例如由第一反相器形成的触发器和与第一反相器交叉耦合的第二反相器。存储元件具有第一和第二端子以及被配置为与第一电源电压互连的存储元件电源电压端子。 WRITE访问设备被配置为在WRITE字线的控制下选择性地将第一终端与WRITE位线互连，并且一对串行READ访问设备被配置为当READ字线活动时将READ位线接地，并且第二终端处于高逻辑级。当将大于第一电源电压的第二电源电压施加到写字线时，基本上不使用互补的写位线，可以将逻辑“1”写入存储元件。

6. 发明授权

US07420836B1 Single-ended memory cell with improved read stability and memory using the cell 有权
标题翻译：单端存储单元，具有改善的读取稳定性和使用单元格的存储器
公开(公告)号：US07420836B1
公开(公告)日：2008-09-02
申请号：US11674292
申请日：2007-02-13
申请人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
发明人： Keunwoo Kim , Rajiv V. Joshi , Vinod Ramadurai
IPC分类号： G11C11/40
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.
摘要翻译：用于与READ和WRITE字线以及READ和WRITE位线互连的存储单元包括逻辑存储元件，例如由第一反相器形成的触发器和与第一反相器交叉耦合的第二反相器。存储元件具有第一和第二端子以及被配置为与第一电源电压互连的存储元件电源电压端子。 WRITE访问设备被配置为在WRITE字线的控制下选择性地将第一终端与WRITE位线互连，并且一对串行READ访问设备被配置为当READ字线活动时将READ位线接地，并且第二终端处于高逻辑级。当将大于第一电源电压的第二电源电压施加到写字线时，基本上不使用互补的写位线，可以将逻辑“1”写入存储元件。

7. 发明申请

US20130289965A1 FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING 有权
公开(公告)号：US20130289965A1
公开(公告)日：2013-10-31
申请号：US13457722
申请日：2012-04-27
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

8. 发明申请

US20130289948A1 FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING 有权
标题翻译：基于快速TCAD变换建模的场效应晶体管
公开(公告)号：US20130289948A1
公开(公告)日：2013-10-31
申请号：US13611359
申请日：2012-09-12
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.
摘要翻译：一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。设备区域提供要分析的感兴趣区域。生成代表性地包括一个或多个设备区域的部分设备。通过采用整个装置结构的物理特性来减少部分装置的分析网格。使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。还披露了系统。

9. 发明授权

US07532501B2 Semiconductor device including back-gated transistors and method of fabricating the device 有权
标题翻译：包括后门控晶体管的半导体器件及其制造方法
公开(公告)号：US07532501B2
公开(公告)日：2009-05-12
申请号：US11142248
申请日：2005-06-02
申请人： Rajiv V. Joshi , Keunwoo Kim , Edward Joseph Nowak , Richard Quimby Williams
发明人： Rajiv V. Joshi , Keunwoo Kim , Edward Joseph Nowak , Richard Quimby Williams
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L29/66795 , H01L29/785
摘要： A memory cell (e.g., static random access memory (SRAM) cell) includes a plurality of back-gated n-type field effect transistors (nFETs), and a plurality of double-gated p-type field effect transistors (pFETs) operatively coupled to the plurality of nFETs.
摘要翻译：存储器单元（例如，静态随机存取存储器（SRAM）单元）包括多个后门控n型场效应晶体管（nFET）和多个双门控p型场效应晶体管（pFET），可操作地耦合到多个nFET。

10. 发明授权

US08515724B2 Technology computer-aided design (TCAD)-based virtual fabrication 失效
标题翻译：技术计算机辅助设计（TCAD）的虚拟制造
公开(公告)号：US08515724B2
公开(公告)日：2013-08-20
申请号：US12820741
申请日：2010-06-22
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F2217/10
摘要： A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD, e.g., finite element) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design, based on the at least one metric determined for each of the parameterized netlists. In at least some instances, an importance sampling technique is tightly integrated with the TCAD process.
摘要翻译：生成单个有限元网格以预测集成电路设计的性能。识别多个采样点用于对与集成电路设计相关联的至少一个参数进行变异性研究。选择采样点以预测由于要用于制造集成电路设计的制造工艺的变化而受到至少一个参数的变化时的集成电路设计的性能。生成对应于每个采样点的参数化网表。对于每个参数化的网表，运行技术计算机辅助设计（TCAD，例如有限元）模拟，使用每个参数化网表的单个有限元网格，直到达到收敛，为每个参数化网表，指示集成电路设计的性能的至少一个度量。基于为每个参数化网表确定的至少一个度量，针对集成电路设计开发了预测的设计收益。在至少一些情况下，重要性采样技术与TCAD过程紧密集成。

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