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1. 发明授权

US08169321B2 Radio frequency-enabled electromigration fuse 有权
标题翻译：射频启用电迁移保险丝
公开(公告)号：US08169321B2
公开(公告)日：2012-05-01
申请号：US12696104
申请日：2010-01-29
申请人： Subramanian S. Iyer , Chandrasekharan Kothandaraman , Gerard M. Salem
发明人： Subramanian S. Iyer , Chandrasekharan Kothandaraman , Gerard M. Salem
IPC分类号： H03K19/00 , G08B13/14
CPC分类号： G01R31/02 , H03K19/173
摘要： Embodiments of the invention provides a method, device, and system for programming an electromigration fuse (eFuse) using a radio frequency (RF) signal. A first aspect of the invention provides a method of testing circuitry on a semiconductor chip, the method comprising: receiving a radio frequency (RF) signal using at least one antenna on the semiconductor chip; powering circuitry on the semiconductor chip using the RF signal; activating a built-in self test (BIST) engine within the circuitry; determining whether a fault exists within the circuitry using the BIST; and programming an electromigration fuse (eFuse) to alter the circuitry in response to a fault being determined to exist.
摘要翻译：本发明的实施例提供了一种使用射频（RF）信号编程电迁移保险丝（eFuse）的方法，装置和系统。本发明的第一方面提供了一种在半导体芯片上测试电路的方法，该方法包括：使用半导体芯片上的至少一个天线接收射频（RF）信号; 使用RF信号对半导体芯片供电; 激活电路内的内置自检（BIST）引擎; 确定使用BIST的电路内是否存在故障; 以及编程电迁移保险丝（eFuse）以响应于确定存在的故障来改变电路。

2. 发明授权

US06643807B1 Array-built-in-self-test (ABIST) for efficient, fast, bitmapping of large embedded arrays in manufacturing test 失效
标题翻译：阵列内置自检（ABIST），用于制造测试中大型嵌入式阵列的高效快速位图
公开(公告)号：US06643807B1
公开(公告)日：2003-11-04
申请号：US09629507
申请日：2000-08-01
申请人： Jay G. Heaslip , Gary W. Maier , Gerard M. Salem , Timothy J. Von Reyn
发明人： Jay G. Heaslip , Gary W. Maier , Gerard M. Salem , Timothy J. Von Reyn
IPC分类号： G11C2900
CPC分类号： G11C29/44 , G11C2207/104
摘要： A structure and method for an integrated circuit which includes read/write memory having a plurality of memory devices, each of the memory devices having a unique address; a built-in self-test (BIST) engine, the BIST engine having a controller responsive to a test enable signal and operative to generate and store test data in the read/write memory; a comparator operative to compare retrieved data read from the read/write memory and the test data during a first pass test, the comparator identifying failed cycles where the retrieved data does not correspond correctly to the test data; and a diagnostic unit operative to store the failed cycles and being responsive to the controller generating and storing the test data in the read/write memory and operative to store failed data and failing addresses during a first pass test, wherein the BIST engine stops only at each of the failed cycles during the first pass test.
摘要翻译：一种用于集成电路的结构和方法，包括具有多个存储器件的读/写存储器，每个存储器件具有唯一的地址; 内置自检（BIST）引擎，BIST引擎具有响应于测试使能信号的控制器，并且可操作地在读/写存储器中生成并存储测试数据; 比较器，用于比较在第一次通过测试期间从读/写存储器读取的检索数据和测试数据，比较器识别检索数据与测试数据不正确对应的故障周期; 以及诊断单元，用于存储故障循环并响应于所述控制器在所述读/写存储器中产生和存储所述测试数据，并且在第一次通过测试期间可操作以存储故障数据和故障地址，其中所述BIST引擎仅在在第一次通过测试期间的每个故障循环。

3. 发明授权

US5844917A Method for testing adapter card ASIC using reconfigurable logic 失效
标题翻译：使用可重配置逻辑测试适配卡ASIC的方法
公开(公告)号：US5844917A
公开(公告)日：1998-12-01
申请号：US831541
申请日：1997-04-08
申请人： Gerard M. Salem , Robert J. Lynch
发明人： Gerard M. Salem , Robert J. Lynch
IPC分类号： G01R31/3185 , G06F11/273 , G01R31/28
CPC分类号： G01R31/318519 , G06F11/273 , G01R31/318516
摘要： An adapter card in a computer system includes an application specific integrated circuit (ASIC) and a field programmable gate array (FPGA) coupled to the ASIC. Random data is provided to the ASIC logic function(s) by control of the FPGA, which is configured by a programmable logic device on the card and coupled thereto. The logic function(s) of the ASIC is then exercised with the random data, and the output is compared with expected output by the system to determine if there are any errors. The determination is made based on a signature produced by a multiple input shift register (MISR) within the ASIC, based on the output data from the logic function(s). The FPGA can then be reconfigured for normal adapter card functions.
摘要翻译：计算机系统中的适配器卡包括专用集成电路（ASIC）和耦合到ASIC的现场可编程门阵列（FPGA）。随机数据通过FPGA的控制提供给ASIC逻辑功能，FPGA由卡上的可编程逻辑器件配置并与其耦合。然后利用随机数据来执行ASIC的逻辑功能，并将输出与系统的预期输出进行比较，以确定是否存在任何错误。基于来自逻辑功能的输出数据，基于由ASIC内的多输入移位寄存器（MISR）产生的签名进行确定。然后可以对FPGA进行重新配置，以进行正常的适配卡功能。

4. 发明授权

US5841790A Apparatus for testing an adapter card ASIC with reconfigurable logic 失效
标题翻译：用于测试具有可重构逻辑的适配器卡ASIC的装置
公开(公告)号：US5841790A
公开(公告)日：1998-11-24
申请号：US831542
申请日：1997-04-08
申请人： Gerard M. Salem , Robert J. Lynch
发明人： Gerard M. Salem , Robert J. Lynch
IPC分类号： G01R31/3185 , G01R31/319 , G01R31/28
CPC分类号： G01R31/31917 , G01R31/318533 , G06F2201/865
摘要： An adapter card in a computer system includes an application specific integrated circuit (ASIC) and a field programmable gate array (FPGA) coupled to the ASIC. Random data is provided to the ASIC logic function(s) by control of the FPGA, which is configured by a programmable logic device on the card and coupled thereto. The logic function(s) of the ASIC is then exercised with the random data, and the output is compared with expected output by the system to determine if there are any errors. The determination is made based on a signature produced by a multiple input shift register (MISR) within the ASIC, based on the output data from the logic function(s). The FPGA can then be reconfigured for normal adapter card functions.
摘要翻译：计算机系统中的适配器卡包括专用集成电路（ASIC）和耦合到ASIC的现场可编程门阵列（FPGA）。随机数据通过FPGA的控制提供给ASIC逻辑功能，FPGA由卡上的可编程逻辑器件配置并与其耦合。然后利用随机数据来执行ASIC的逻辑功能，并将输出与系统的预期输出进行比较，以确定是否存在任何错误。基于来自逻辑功能的输出数据，基于由ASIC内的多输入移位寄存器（MISR）产生的签名进行确定。然后可以对FPGA进行重新配置，以进行正常的适配卡功能。

5. 发明申请

US20110320716A1 LOADING AND UNLOADING A MEMORY ELEMENT FOR DEBUG 失效
标题翻译：装载和卸载记忆元素进行调试
公开(公告)号：US20110320716A1
公开(公告)日：2011-12-29
申请号：US12822882
申请日：2010-06-24
申请人： Adam B. Collura , Michael Fee , Arthur J. O'Neill, JR. , Gerard M. Salem , Robert J. Sonnelitter, III
发明人： Adam B. Collura , Michael Fee , Arthur J. O'Neill, JR. , Gerard M. Salem , Robert J. Sonnelitter, III
IPC分类号： G06F12/08
CPC分类号： G06F11/073 , G06F11/0751
摘要： A method of debugging a memory element is provided. The method includes initializing a line fetch controller with at least one of write data and read data; utilizing at least two separate clocks for performing at least one of write requests and read requests based on the at least one of the write data and the read data; and debugging the memory element based on the at least one of write requests and read requests.
摘要翻译：提供了一种调试存储元件的方法。该方法包括：利用写入数据和读取数据中的至少一个初始化线取指控制器; 利用至少两个分离的时钟，用于基于写数据和读数据中的至少一个来执行写请求和读请求中的至少一个; 以及基于写入请求和读取请求中的至少一个来调试所述存储器元件。

6. 发明授权

US5544088A Method of I/O pin assignment in a hierarchial packaging system 失效
标题翻译：分层包装系统中I / O引脚分配的方法
公开(公告)号：US5544088A
公开(公告)日：1996-08-06
申请号：US492415
申请日：1995-06-19
申请人： Matthew E. Aubertine , Kianoush Beyzavi , Harold J. Broker , Ronald P. Checca , Michael A. Granato , David A. Haeussler , Michael Herasimtschuk , Michael J. Jurkovic , Gerard M. Salem , Craig R. Selinger , Paul R. Zehr
发明人： Matthew E. Aubertine , Kianoush Beyzavi , Harold J. Broker , Ronald P. Checca , Michael A. Granato , David A. Haeussler , Michael Herasimtschuk , Michael J. Jurkovic , Gerard M. Salem , Craig R. Selinger , Paul R. Zehr
IPC分类号： G06F13/40 , G06F17/50 , G06F15/17 , G06F11/26
CPC分类号： G06F13/4072 , G06F17/5072
摘要： A method is provided to assign component I/O (input/output, the interface area between levels of physical packaging) pins for all components at each level of the computer system. In a hierarchical, top-down design methodology, the I/O pins for each computer system component are assigned to nets (a net is an interconnection of pins on a level of packaging, or between levels of packaging) based on wire length, electrical limits and timing. Parameters that are considered are net priority (the importance of this net to the system, relative to other nets in the system), location of physical components, location of physical component I/Os at all computer system levels of physical packaging hierarchy, and I/O pin characteristics. An iterative method is used to assign and reassign I/O pins at each level based on timing. As I/Os are reassigned at each lower component level, new assignments are made at all higher levels of the system packaging hierarchy based on the changed parameters at the lower level. I/Os assignment by this method for a computer system package design reduces the occurance of any critical nets failing length, electrical or timing constraints due to poor I/O assignments. The method has built in checks to avoid being trapped in an NP complete situation (a form of endless loop).
摘要翻译：提供了一种方法来为计算机系统的每个级别的所有组件分配组件I / O（输入/输出，物理封装级别之间的接口面积）引脚。在分层的自上而下的设计方法中，每个计算机系统组件的I / O引脚分配给网络（网络是包装级别的引脚或封装层级之间的互连），基于导线长度，电气限制和时间安排被考虑的参数是网络优先级（该网络对系统的相对于系统中的其他网络的重要性），物理组件的位置，物理组件I / O在物理包装层次结构的所有计算机系统级别的位置，以及I / O引脚特性。使用迭代方法根据时序分配和重新分配每个级别的I / O引脚。由于I / O在每个较低的组件级别重新分配，所以根据较低级别的已更改参数在系统打包层次结构的所有较高级别进行新的分配。通过该方法对计算机系统软件包设计进行的I / O分配可以减少由于I / O分配不良导致的任何关键网络发生长度，电气或时序限制的故障。该方法已经内置了检查，以避免被困在NP完全情况（一种无止境循环的形式）中。

7. 发明授权

US08977895B2 Multi-core diagnostics and repair using firmware and spare cores 有权
标题翻译：使用固件和备用内核进行多核诊断和修复
公开(公告)号：US08977895B2
公开(公告)日：2015-03-10
申请号：US13552237
申请日：2012-07-18
申请人： Sreekala Anandavally , Anand Haridass , Gerard M. Salem , Diyanesh B. C. Vidyapoornachary
发明人： Sreekala Anandavally , Anand Haridass , Gerard M. Salem , Diyanesh B. C. Vidyapoornachary
IPC分类号： G06F11/00 , G06F11/16
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/079 , G06F11/1428 , G06F11/16 , G06F11/2028 , G06F11/2041
摘要： Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.
摘要翻译：本公开的实施例涉及一种装置，其包括易受错误状况影响的第一核心，以及第二核心，被配置为对第一核心执行诊断以识别错误状况的原因以及纠正错误状况的动作命令恢复第一核心。

8. 发明申请

US20110187407A1 RADIO FREQUENCY-ENABLED ELECTROMIGRATION FUSE 有权
标题翻译：无线电频率电磁保险丝
公开(公告)号：US20110187407A1
公开(公告)日：2011-08-04
申请号：US12696104
申请日：2010-01-29
申请人： Subramanian S. Iyer , Chandrasekharan Kothandaraman , Gerard M. Salem
发明人： Subramanian S. Iyer , Chandrasekharan Kothandaraman , Gerard M. Salem
IPC分类号： H03K19/173 , G01R31/02
CPC分类号： G01R31/02 , H03K19/173
摘要： Embodiments of the invention provides a method, device, and system for programming an electromigration fuse (eFuse) using a radio frequency (RF) signal. A first aspect of the invention provides a method of testing circuitry on a semiconductor chip, the method comprising: receiving a radio frequency (RF) signal using at least one antenna on the semiconductor chip; powering circuitry on the semiconductor chip using the RF signal; activating a built-in self test (BIST) engine within the circuitry; determining whether a fault exists within the circuitry using the BIST; and programming an electromigration fuse (eFuse) to alter the circuitry in response to a fault being determined to exist.
摘要翻译：本发明的实施例提供了一种使用射频（RF）信号编程电迁移保险丝（eFuse）的方法，装置和系统。本发明的第一方面提供了一种在半导体芯片上测试电路的方法，该方法包括：使用半导体芯片上的至少一个天线接收射频（RF）信号; 使用RF信号对半导体芯片供电; 激活电路内的内置自检（BIST）引擎; 确定使用BIST的电路内是否存在故障; 以及编程电迁移保险丝（eFuse）以响应于确定存在的故障来改变电路。

9. 发明授权

US06989696B2 System and method for synchronizing divide-by counters 失效
标题翻译：用于同步分频计数器的系统和方法
公开(公告)号：US06989696B2
公开(公告)日：2006-01-24
申请号：US10707066
申请日：2003-11-19
申请人： Rolf Hilgendorf , Jens Kuenzer , Cédric Lichtenau , Thomas Pflueger , Mathew I. Ringler , Gerard M. Salem , Peter A. Sandon , Dana J. Thygesen , Ulrich Weiss
发明人： Rolf Hilgendorf , Jens Kuenzer , Cédric Lichtenau , Thomas Pflueger , Mathew I. Ringler , Gerard M. Salem , Peter A. Sandon , Dana J. Thygesen , Ulrich Weiss
IPC分类号： H03L7/00
CPC分类号： H03L7/06
摘要： A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.
摘要翻译：能够将多个处理器（A，B）的频率分频计数器（124A，124BB）同时复位的同步系统为零，而不管分频频率信号（Mclk / n信号（168A，168B）），并且与处理器中的Mclk / n信号经历的时钟网格延迟的大小无关。同步系统包括用于在未分割信号中模拟的每个处理器的网格延迟电路（176A，176BB）（Mclk / 1信号（136 < / SUB>，136 B））由该处理器中的Mclk / n信号经历的时钟网格延迟，以便提供Lclk信号（172 ，172 _{B ）。相位检测器检测Mclk / n信号和Sysclk信号之间的相位偏移（112），并将异步偏移信号（194A，192B）发送到计数器基于偏移信号将再分配计数器复位为零的重新设置器（196A，196BB）。}

10. 发明授权

US07194715B2 Method and system for performing static timing analysis on digital electronic circuits 失效
标题翻译：在数字电子电路上执行静态时序分析的方法和系统
公开(公告)号：US07194715B2
公开(公告)日：2007-03-20
申请号：US10709376
申请日：2004-04-30
申请人： Steven E. Charlebois , Gerard M. Salem
发明人： Steven E. Charlebois , Gerard M. Salem
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for performing static timing analysis on digital electronic circuits is disclosed. A snip (or DC adjust) file is initially generated. Static timing analysis is then performed on the final circuit netlist using the snip file. If the final circuit netlist meets all the timing constraints, the snip file is converted to a group of cutpoints, and formal verification is performed on the cutpoints. A determination is made as to whether or not the cutpoints pass formal verification. If the cutpoints pass formal verification, the user analysis on the final circuit netlist is completed, and the final circuit netlist can proceed to manufacturing. Otherwise, if the cutpoints do not pass formal verification, a flag is issued to alert a user. The user then has to either modify certain snip point(s) within the snip file or modify the circuit netlist, and perform the user analysis again.
摘要翻译：公开了一种在数字电子电路上执行静态时序分析的方法。最初生成剪辑（或DC调整）文件。然后使用snip文件在最终的电路网表上执行静态时序分析。如果最终的电路网表满足所有的时序限制，则将snip文件转换成一组切点，并对切点执行形式验证。决定切点是否通过正式验证。如果切点通过正式验证，则完成最终电路网表上的用户分析，最后的电路网表可以进行制造。否则，如果切点没有通过正式验证，则会发出一个标志来提醒用户。然后，用户必须修改snip文件中的某些剪切点或修改电路网表，并再次执行用户分析。

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