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    • 2. 发明授权
    • Array-built-in-self-test (ABIST) for efficient, fast, bitmapping of large embedded arrays in manufacturing test
    • 阵列内置自检(ABIST),用于制造测试中大型嵌入式阵列的高效快速位图
    • US06643807B1
    • 2003-11-04
    • US09629507
    • 2000-08-01
    • Jay G. HeaslipGary W. MaierGerard M. SalemTimothy J. Von Reyn
    • Jay G. HeaslipGary W. MaierGerard M. SalemTimothy J. Von Reyn
    • G11C2900
    • G11C29/44G11C2207/104
    • A structure and method for an integrated circuit which includes read/write memory having a plurality of memory devices, each of the memory devices having a unique address; a built-in self-test (BIST) engine, the BIST engine having a controller responsive to a test enable signal and operative to generate and store test data in the read/write memory; a comparator operative to compare retrieved data read from the read/write memory and the test data during a first pass test, the comparator identifying failed cycles where the retrieved data does not correspond correctly to the test data; and a diagnostic unit operative to store the failed cycles and being responsive to the controller generating and storing the test data in the read/write memory and operative to store failed data and failing addresses during a first pass test, wherein the BIST engine stops only at each of the failed cycles during the first pass test.
    • 一种用于集成电路的结构和方法,包括具有多个存储器件的读/写存储器,每个存储器件具有唯一的地址; 内置自检(BIST)引擎,BIST引擎具有响应于测试使能信号的控制器,并且可操作地在读/写存储器中生成并存储测试数据; 比较器,用于比较在第一次通过测试期间从读/写存储器读取的检索数据和测试数据,比较器识别检索数据与测试数据不正确对应的故障周期; 以及诊断单元,用于存储故障循环并响应于所述控制器在所述读/写存储器中产生和存储所述测试数据,并且在第一次通过测试期间可操作以存储故障数据和故障地址,其中所述BIST引擎仅在 在第一次通过测试期间的每个故障循环。
    • 3. 发明授权
    • Method for testing adapter card ASIC using reconfigurable logic
    • 使用可重配置逻辑测试适配卡ASIC的方法
    • US5844917A
    • 1998-12-01
    • US831541
    • 1997-04-08
    • Gerard M. SalemRobert J. Lynch
    • Gerard M. SalemRobert J. Lynch
    • G01R31/3185G06F11/273G01R31/28
    • G01R31/318519G06F11/273G01R31/318516
    • An adapter card in a computer system includes an application specific integrated circuit (ASIC) and a field programmable gate array (FPGA) coupled to the ASIC. Random data is provided to the ASIC logic function(s) by control of the FPGA, which is configured by a programmable logic device on the card and coupled thereto. The logic function(s) of the ASIC is then exercised with the random data, and the output is compared with expected output by the system to determine if there are any errors. The determination is made based on a signature produced by a multiple input shift register (MISR) within the ASIC, based on the output data from the logic function(s). The FPGA can then be reconfigured for normal adapter card functions.
    • 计算机系统中的适配器卡包括专用集成电路(ASIC)和耦合到ASIC的现场可编程门阵列(FPGA)。 随机数据通过FPGA的控制提供给ASIC逻辑功能,FPGA由卡上的可编程逻辑器件配置并与其耦合。 然后利用随机数据来执行ASIC的逻辑功能,并将输出与系统的预期输出进行比较,以确定是否存在任何错误。 基于来自逻辑功能的输出数据,基于由ASIC内的多输入移位寄存器(MISR)产生的签名进行确定。 然后可以对FPGA进行重新配置,以进行正常的适配卡功能。
    • 4. 发明授权
    • Apparatus for testing an adapter card ASIC with reconfigurable logic
    • 用于测试具有可重构逻辑的适配器卡ASIC的装置
    • US5841790A
    • 1998-11-24
    • US831542
    • 1997-04-08
    • Gerard M. SalemRobert J. Lynch
    • Gerard M. SalemRobert J. Lynch
    • G01R31/3185G01R31/319G01R31/28
    • G01R31/31917G01R31/318533G06F2201/865
    • An adapter card in a computer system includes an application specific integrated circuit (ASIC) and a field programmable gate array (FPGA) coupled to the ASIC. Random data is provided to the ASIC logic function(s) by control of the FPGA, which is configured by a programmable logic device on the card and coupled thereto. The logic function(s) of the ASIC is then exercised with the random data, and the output is compared with expected output by the system to determine if there are any errors. The determination is made based on a signature produced by a multiple input shift register (MISR) within the ASIC, based on the output data from the logic function(s). The FPGA can then be reconfigured for normal adapter card functions.
    • 计算机系统中的适配器卡包括专用集成电路(ASIC)和耦合到ASIC的现场可编程门阵列(FPGA)。 随机数据通过FPGA的控制提供给ASIC逻辑功能,FPGA由卡上的可编程逻辑器件配置并与其耦合。 然后利用随机数据来执行ASIC的逻辑功能,并将输出与系统的预期输出进行比较,以确定是否存在任何错误。 基于来自逻辑功能的输出数据,基于由ASIC内的多输入移位寄存器(MISR)产生的签名进行确定。 然后可以对FPGA进行重新配置,以进行正常的适配卡功能。
    • 6. 发明授权
    • Method of I/O pin assignment in a hierarchial packaging system
    • 分层包装系统中I / O引脚分配的方法
    • US5544088A
    • 1996-08-06
    • US492415
    • 1995-06-19
    • Matthew E. AubertineKianoush BeyzaviHarold J. BrokerRonald P. CheccaMichael A. GranatoDavid A. HaeusslerMichael HerasimtschukMichael J. JurkovicGerard M. SalemCraig R. SelingerPaul R. Zehr
    • Matthew E. AubertineKianoush BeyzaviHarold J. BrokerRonald P. CheccaMichael A. GranatoDavid A. HaeusslerMichael HerasimtschukMichael J. JurkovicGerard M. SalemCraig R. SelingerPaul R. Zehr
    • G06F13/40G06F17/50G06F15/17G06F11/26
    • G06F13/4072G06F17/5072
    • A method is provided to assign component I/O (input/output, the interface area between levels of physical packaging) pins for all components at each level of the computer system. In a hierarchical, top-down design methodology, the I/O pins for each computer system component are assigned to nets (a net is an interconnection of pins on a level of packaging, or between levels of packaging) based on wire length, electrical limits and timing. Parameters that are considered are net priority (the importance of this net to the system, relative to other nets in the system), location of physical components, location of physical component I/Os at all computer system levels of physical packaging hierarchy, and I/O pin characteristics. An iterative method is used to assign and reassign I/O pins at each level based on timing. As I/Os are reassigned at each lower component level, new assignments are made at all higher levels of the system packaging hierarchy based on the changed parameters at the lower level. I/Os assignment by this method for a computer system package design reduces the occurance of any critical nets failing length, electrical or timing constraints due to poor I/O assignments. The method has built in checks to avoid being trapped in an NP complete situation (a form of endless loop).
    • 提供了一种方法来为计算机系统的每个级别的所有组件分配组件I / O(输入/输出,物理封装级别之间的接口面积)引脚。 在分层的自上而下的设计方法中,每个计算机系统组件的I / O引脚分配给网络(网络是包装级别的引脚或封装层级之间的互连),基于导线长度,电气 限制和时间安排 被考虑的参数是网络优先级(该网络对系统的相对于系统中的其他网络的重要性),物理组件的位置,物理组件I / O在物理包装层次结构的所有计算机系统级别的位置,以及I / O引脚特性。 使用迭代方法根据时序分配和重新分配每个级别的I / O引脚。 由于I / O在每个较低的组件级别重新分配,所以根据较低级别的已更改参数在系统打包层次结构的所有较高级别进行新的分配。 通过该方法对计算机系统软件包设计进行的I / O分配可以减少由于I / O分配不良导致的任何关键网络发生长度,电气或时序限制的故障。 该方法已经内置了检查,以避免被困在NP完全情况(一种无止境循环的形式)中。
    • 10. 发明授权
    • Method and system for performing static timing analysis on digital electronic circuits
    • 在数字电子电路上执行静态时序分析的方法和系统
    • US07194715B2
    • 2007-03-20
    • US10709376
    • 2004-04-30
    • Steven E. CharleboisGerard M. Salem
    • Steven E. CharleboisGerard M. Salem
    • G06F17/50
    • G06F17/5031
    • A method for performing static timing analysis on digital electronic circuits is disclosed. A snip (or DC adjust) file is initially generated. Static timing analysis is then performed on the final circuit netlist using the snip file. If the final circuit netlist meets all the timing constraints, the snip file is converted to a group of cutpoints, and formal verification is performed on the cutpoints. A determination is made as to whether or not the cutpoints pass formal verification. If the cutpoints pass formal verification, the user analysis on the final circuit netlist is completed, and the final circuit netlist can proceed to manufacturing. Otherwise, if the cutpoints do not pass formal verification, a flag is issued to alert a user. The user then has to either modify certain snip point(s) within the snip file or modify the circuit netlist, and perform the user analysis again.
    • 公开了一种在数字电子电路上执行静态时序分析的方法。 最初生成剪辑(或DC调整)文件。 然后使用snip文件在最终的电路网表上执行静态时序分析。 如果最终的电路网表满足所有的时序限制,则将snip文件转换成一组切点,并对切点执行形式验证。 决定切点是否通过正式验证。 如果切点通过正式验证,则完成最终电路网表上的用户分析,最后的电路网表可以进行制造。 否则,如果切点没有通过正式验证,则会发出一个标志来提醒用户。 然后,用户必须修改snip文件中的某些剪切点或修改电路网表,并再次执行用户分析。