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1. 发明授权

US06591388B1 High speed sink/source register to reduce level sensitive scan design test time 失效
标题翻译：高速吸收/源寄存器，以降低敏感扫描设计的测试时间
公开(公告)号：US06591388B1
公开(公告)日：2003-07-08
申请号：US09551130
申请日：2000-04-18
申请人： Timothy J. Vonreyn
发明人： Timothy J. Vonreyn
IPC分类号： G01R3128
CPC分类号： G01R31/318536 , G01R31/318544
摘要： Test data is provided through shift registers, operated at a high clock rate comparable to or exceeding a normal high speed clock rate of a chip being tested, to each of a plurality of scan chains configured from registers present on the chip; respective latches of which are connected to inputs and outputs of logic array partitions to be tested. Reduced test clock rate of input and output circuits of the scan chains is accommodated by high speed source and sink shift registers. The source and sink registers are fully loaded and unloaded between consecutive test clock signals and test signals are preferably applied to and collected from the chip in a single serial string through a single pair of tester input/output pins. Testing time is thus reduced without requiring design time and chip space for a clock tree optimized for high speed operation while use of testers of reduced cost and having an arbitrarily small number of input/output pin pairs and independent of test register configuaration on the chip can be used.
摘要翻译：通过移位寄存器提供测试数据，该移位寄存器以与正在测试的芯片的正常高速时钟速率相当或者超过正在被测试的芯片的正常高速时钟速率的高时钟速率被提供给由存在于芯片上的寄存器配置的多个扫描链中的每其相应的锁存器连接到要测试的逻辑阵列分区的输入和输出。降低扫描链的输入和输出电路的测试时钟速率由高速源和吸收移位寄存器来适应。源和宿寄存器在连续的测试时钟信号之间被完全加载和卸载，并且测试信号优选地通过单个测试器输入/输出引脚在单个串行串中被施加到芯片并从芯片采集。因此，降低了测试时间，而不需要为高速操作优化的时钟树的设计时间和芯片空间，同时使用降低成本的测试仪，并且具有任意少量的输入/输出引脚对，并且独立于芯片上的测试寄存器配置使用。

2. 发明授权

US07042776B2 Method and circuit for dynamic read margin control of a memory array 失效
标题翻译：存储器阵列的动态读取余量控制的方法和电路
公开(公告)号：US07042776B2
公开(公告)日：2006-05-09
申请号：US10708236
申请日：2004-02-18
申请人： Miles G. Canada , Stephen F. Geissler , Robert M. Houle , Dongho Lee , Vinod Ramadurai , Mathew I. Ringler , Gerard M. Salem , Timothy J. Vonreyn
发明人： Miles G. Canada , Stephen F. Geissler , Robert M. Houle , Dongho Lee , Vinod Ramadurai , Mathew I. Ringler , Gerard M. Salem , Timothy J. Vonreyn
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/1045 , G11C2207/065 , G11C2207/2254
摘要： A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.
摘要翻译：一种用于调整自定时存储器阵列的读取余量的方法和电路。该电子电路包括：存储单元阵列，包括适于设置存储单元阵列的基本读时间延迟的读出放大器自定时解码电路; 以及耦合到所述存储单元阵列的读延迟调整电路，所述读延迟调整电路适于基于所述存储单元阵列的工作频率来调整所述存储器阵列的基本读时间延迟。

3. 发明授权

US5564042A Asynchronous clock switching between first and second clocks by extending phase of current clock and switching after a predetermined time and appropriated transitions 失效
标题翻译：通过延长当前时钟的相位并在预定时间和适当的转换之后切换，在第一和第二时钟之间进行异步时钟切换
公开(公告)号：US5564042A
公开(公告)日：1996-10-08
申请号：US191446
申请日：1994-02-03
申请人： Sebastian T. Ventrone , Timothy J. VonReyn
发明人： Sebastian T. Ventrone , Timothy J. VonReyn
IPC分类号： G06F1/06 , G06F1/08 , G06F9/30 , G06F13/42 , G06F1/04
CPC分类号： G06F1/08
摘要： A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entry signals intent to use the bus.A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entity signals intent to use the bus.
摘要翻译：具有两个板上时钟发生器的微处理器。更快的时钟发生器在正常的同步模式下控制微处理器。当总线必须被访问时，较慢的时钟发生器控制微处理器，或者在“窥探”模式时，当另一个输入信号意图使用总线时被调用。具有两个板上时钟发生器的微处理器。更快的时钟发生器在正常的同步模式下控制微处理器。当总线必须被访问时，较慢的时钟发生器控制微处理器，或者在另一个实体发出意图使用总线时调用的“窥探”模式。

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