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1. 发明授权

US06820143B2 On-chip data transfer in multi-processor system 失效
标题翻译：多处理器系统中的片上数据传输
公开(公告)号：US06820143B2
公开(公告)日：2004-11-16
申请号：US10322127
申请日：2002-12-17
申请人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichun Peter Liu , David Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichun Peter Liu , David Shippy , Thuong Quang Truong
IPC分类号： G06F1328
CPC分类号： G06F12/0817 , G06F12/0897
摘要： A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.
摘要翻译：提供了一种通过在不同处理器之间提供直接数据传输来提高计算机系统的性能的系统和方法。该系统包括第一和第二处理器。第一个处理器需要数据。该系统还包括与第一处理器通信的目录。目录接收到数据的数据请求，并包含有关数据存储位置的信息。缓存耦合到第二处理器。当发现数据被存储在高速缓存中时，内部总线耦合在第一处理器和高速缓存之间以将数据从高速缓存传送到第一处理器。

2. 发明授权

US07114035B2 Software-controlled cache set management with software-generated class identifiers 失效
标题翻译：软件控制的缓存集管理与软件生成的类标识符
公开(公告)号：US07114035B2
公开(公告)日：2006-09-26
申请号：US10655365
申请日：2003-09-04
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.
摘要翻译：本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。根据地址未命中创建类标识符。替换管理表可用于读取类标识符以创建标签替换控制标记。包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

3. 发明授权

US07103748B2 Memory management for real-time applications 失效
标题翻译：内存管理用于实时应用
公开(公告)号：US07103748B2
公开(公告)日：2006-09-05
申请号：US10318541
申请日：2002-12-12
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
IPC分类号： G06F12/12
CPC分类号： G06F12/1027 , G06F12/126
摘要： Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.
摘要翻译：计算机系统中的存储器管理通过防止地址转换信息的一部分被替换为高速缓冲存储器中的其他类型的地址转换信息而被改进，该高速缓冲存储器被保留用于存储用于CPU更快速访问的这种地址转换信息。这样，CPU可以识别存储在高速缓存中的地址转换信息的子集。

4. 发明授权

US06981072B2 Memory management in multiprocessor system 失效
标题翻译：多处理器系统中的内存管理
公开(公告)号：US06981072B2
公开(公告)日：2005-12-27
申请号：US10455169
申请日：2003-06-05
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
IPC分类号： G06F12/10 , G06F13/00 , G06F13/28
CPC分类号： G06F13/28 , G06F12/1081
摘要： A system and a method are provided for improving memory management in a multiprocessor system. A direct memory access (DMA) operation is set up for a first processor. A DMA effective address is translated to a virtual address. The virtual address is translated to a physical address, which is used to access a memory hierarchy of the multiprocessor system.
摘要翻译：提供了一种用于改善多处理器系统中的存储器管理的系统和方法。为第一个处理器设置直接存储器访问（DMA）操作。 DMA有效地址转换为虚拟地址。虚拟地址被转换为物理地址，用于访问多处理器系统的存储器层次结构。

5. 发明授权

US07120748B2 Software-controlled cache set management 失效
标题翻译：软件控制缓存集管理
公开(公告)号：US07120748B2
公开(公告)日：2006-10-10
申请号：US10655367
申请日：2003-09-04
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Roy Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Roy Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： The present invention provides a system for managing cache replacement eligibility. A first address register is configured to request an address from an L1 cache. An L1 cache is configured to determine whether a requested address is in the L1 cache and, in response to a determination that a requested address is not in the L1 cache, is further configured to transmit the requested address to a range register coupled to the L1 cache. The range register is configured to generate a class identifier in response to a received requested address and to transmit the requested address and class identifier to a replacement management table coupled to the range register. The replacement management table is configured to generate L2 tag replacement control indicia in response to a received requested address and class identifier. An L2 address register is coupled to the first address register and configured to request an address from an L2 cache. An L2 cache is coupled to the L2 address register and the replacement management table and is configured to determine whether a requested address is in the L2 cache and is further configured to assign replacement eligibility of at least one set of cache lines in the L2 cache in response to received L2 tag replacement control indicia. In response to a determination that a requested address is not in the L2 cache, the L2 cache is further configured to overwrite a cache line within a set of the L2 cache as a function of the replacement eligibility.
摘要翻译：本发明提供了一种用于管理高速缓存替换资格的系统。第一地址寄存器被配置为从L1高速缓存请求地址。 L1缓存被配置为确定所请求的地址是否在L1高速缓存中，并且响应于所请求的地址不在L1高速缓存中的确定，还被配置为将所请求的地址发送到耦合到L1的范围寄存器缓存。范围寄存器被配置为响应于接收到的请求的地址生成类标识符，并将所请求的地址和类标识符发送到耦合到范围寄存器的替换管理表。替换管理表被配置为响应于接收到的请求的地址和类标识符来生成L2标签替换控制标记。 L2地址寄存器耦合到第一地址寄存器并且被配置为从L2高速缓存请求地址。 L2缓存耦合到L2地址寄存器和替换管理表，并且被配置为确定所请求的地址是否在L2高速缓存中，并被进一步配置为在L2高速缓存中分配至少一组高速缓存行的替换资格响应接收的L2标签替换控制标记。响应于所请求的地址不在L2高速缓存中的确定，L2高速缓存进一步被配置为根据替换资格来覆盖L2高速缓存中的高速缓存行。

6. 发明授权

US07953960B2 Method and apparatus for delaying a load miss flush until issuing the dependent instruction 有权
标题翻译：用于延迟负载奇偶校验的方法和装置，直到发出依赖指令
公开(公告)号：US07953960B2
公开(公告)日：2011-05-31
申请号：US11252410
申请日：2005-10-18
申请人： Kurt Alan Feiste , David Scott Ray , David Shippy , Albert James Van Norstrand, Jr.
发明人： Kurt Alan Feiste , David Scott Ray , David Shippy , Albert James Van Norstrand, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3859 , G06F9/3861 , G06F9/3867
摘要： A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access instruction progresses down the pipeline and when the flush stage is reached, the processor checks the associated bit and flushes the register access instruction.
摘要翻译：流水线处理器具有在管线的发布阶段检测寄存器访问指令的存在的电路。在稍后阶段发生的负载丢失可能导致寄存器访问指令被标记有相关位。寄存器访问指令在流水线下进行，当达到flush阶段时，处理器检查相关的位并刷新寄存器访问指令。

7. 发明授权

US07913070B2 Time-of-life counter for handling instruction flushes from a queue 有权
标题翻译：处理指令的生命周期计数器从队列中刷新
公开(公告)号：US07913070B2
公开(公告)日：2011-03-22
申请号：US12250285
申请日：2008-10-13
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
IPC分类号： G06F7/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.
摘要翻译：介绍使用计数器跟踪发出的指令的顺序。在一个实施例中，使用饱和的递减计数器。计数器初始化为与处理器提交点对应的值。指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。一旦计数器达到零，将由执行单元完成。如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。

8. 发明授权

US07831808B2 Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor 有权
标题翻译：队列设计系统支持通用处理器中的SIMD指令的依赖性检查和问题
公开(公告)号：US07831808B2
公开(公告)日：2010-11-09
申请号：US11961914
申请日：2007-12-20
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , David Shippy
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3859 , G06F9/3885 , G06F9/3887
摘要： A processor includes a general purpose (GP) unit adapted to receive and configured to execute GP instructions; and includes a single instruction multiple data (SIMD) unit adapted to receive and configured to execute SIMD instructions. An instruction unit comprises a first logic unit coupled to the GP unit and a second logic unit coupled to the SIMD unit, wherein SIMD instructions are processed subsequent to GP instructions. In the first logic unit a GP instruction with unresolved dependencies unconditionally causes subsequent SIMD instructions to stall, and an SIMD instruction with unresolved dependencies does not cause subsequent GP instructions to stall. The first logic unit resolves dependencies in GP instructions, provides dependency-free instructions to the GP unit, and provides SIMD instructions to the second logic unit. The second logic unit resolves dependencies in SIMD instructions and provides dependency-free instructions to the SIMD unit.
摘要翻译：处理器包括适于接收和配置为执行GP指令的通用（GP）单元; 并且包括适于接收和配置为执行SIMD指令的单指令多数据（SIMD）单元。指令单元包括耦合到GP单元的第一逻辑单元和耦合到SIMD单元的第二逻辑单元，其中在GP指令之后处理SIMD指令。在第一个逻辑单元中，具有未解决的依赖关系的GP指令无条件地导致后续的SIMD指令停止，并且具有未解决依赖性的SIMD指令不会导致后续的GP指令停止。第一个逻辑单元解决GP指令中的依赖关系，向GP单元提供无依赖指令，并向第二个逻辑单元提供SIMD指令。第二个逻辑单元解决SIMD指令中的依赖关系，并向SIMD单元提供无依赖指令。

9. 发明授权

US07490224B2 Time-of-life counter design for handling instruction flushes from a queue 失效
标题翻译：处理指令从队列刷新的生命周期计数器设计
公开(公告)号：US07490224B2
公开(公告)日：2009-02-10
申请号：US11246587
申请日：2005-10-07
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.
摘要翻译：介绍使用计数器跟踪发出的指令的顺序。在一个实施例中，使用饱和的递减计数器。计数器初始化为与处理器提交点对应的值。指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。一旦计数器达到零，将由执行单元完成。如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。

10. 发明授权

US07313673B2 Fine grained multi-thread dispatch block mechanism 有权
标题翻译：细粒度多线程调度块机制
公开(公告)号：US07313673B2
公开(公告)日：2007-12-25
申请号：US11154158
申请日：2005-06-16
申请人： Christopher Michael Abernathy , Jonathan James Dement , Albert James Van Norstrand, Jr. , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James Dement , Albert James Van Norstrand, Jr. , David Shippy
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/3009 , G06F9/3802
摘要： The present invention provides a method, a computer program product, and an apparatus for blocking a thread at dispatch in a multi-thread processor for fine-grained control of thread performance. Multiple threads share a pipeline within a processor. Therefore, a long latency condition for an instruction on one thread can stall all of the threads that share the pipeline. A dispatch-block signaling instruction blocks the thread containing the long latency condition at dispatch. The length of the block matches the length of the latency, so the pipeline can dispatch instructions from the blocked thread after the long latency condition is resolved. In one embodiment the dispatch-block signaling instruction is a modified OR instruction and in another embodiment it is a Nop instruction. By blocking one thread at dispatch, the processor can dispatch instructions from the other threads during the block.
摘要翻译：本发明提供一种方法，计算机程序产品和用于在多线程处理器中调度线程的线程的装置，用于线程性能的细粒度控制。多个线程在处理器中共享流水线。因此，一个线程上的指令的长延迟条件可以阻止所有共享流水线的线程。调度块信令指令在发送时阻止包含长延迟条件的线程。块的长度与延迟的长度相匹配，因此，在长时间等待条件解决之后，流水线可以从阻塞的线程中分派指令。在一个实施例中，调度块信令指令是经修改的OR指令，在另一实施例中是Nop指令。通过在调度时阻止一个线程，处理器可以在块期间从其他线程分派指令。

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