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1. 发明授权

US07114035B2 Software-controlled cache set management with software-generated class identifiers 失效
标题翻译：软件控制的缓存集管理与软件生成的类标识符
公开(公告)号：US07114035B2
公开(公告)日：2006-09-26
申请号：US10655365
申请日：2003-09-04
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.
摘要翻译：本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。根据地址未命中创建类标识符。替换管理表可用于读取类标识符以创建标签替换控制标记。包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

2. 发明授权

US07103748B2 Memory management for real-time applications 失效
标题翻译：内存管理用于实时应用
公开(公告)号：US07103748B2
公开(公告)日：2006-09-05
申请号：US10318541
申请日：2002-12-12
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
IPC分类号： G06F12/12
CPC分类号： G06F12/1027 , G06F12/126
摘要： Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.
摘要翻译：计算机系统中的存储器管理通过防止地址转换信息的一部分被替换为高速缓冲存储器中的其他类型的地址转换信息而被改进，该高速缓冲存储器被保留用于存储用于CPU更快速访问的这种地址转换信息。这样，CPU可以识别存储在高速缓存中的地址转换信息的子集。

3. 发明授权

US06981072B2 Memory management in multiprocessor system 失效
标题翻译：多处理器系统中的内存管理
公开(公告)号：US06981072B2
公开(公告)日：2005-12-27
申请号：US10455169
申请日：2003-06-05
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
IPC分类号： G06F12/10 , G06F13/00 , G06F13/28
CPC分类号： G06F13/28 , G06F12/1081
摘要： A system and a method are provided for improving memory management in a multiprocessor system. A direct memory access (DMA) operation is set up for a first processor. A DMA effective address is translated to a virtual address. The virtual address is translated to a physical address, which is used to access a memory hierarchy of the multiprocessor system.
摘要翻译：提供了一种用于改善多处理器系统中的存储器管理的系统和方法。为第一个处理器设置直接存储器访问（DMA）操作。 DMA有效地址转换为虚拟地址。虚拟地址被转换为物理地址，用于访问多处理器系统的存储器层次结构。

4. 发明授权

US07120748B2 Software-controlled cache set management 失效
标题翻译：软件控制缓存集管理
公开(公告)号：US07120748B2
公开(公告)日：2006-10-10
申请号：US10655367
申请日：2003-09-04
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Roy Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Roy Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： The present invention provides a system for managing cache replacement eligibility. A first address register is configured to request an address from an L1 cache. An L1 cache is configured to determine whether a requested address is in the L1 cache and, in response to a determination that a requested address is not in the L1 cache, is further configured to transmit the requested address to a range register coupled to the L1 cache. The range register is configured to generate a class identifier in response to a received requested address and to transmit the requested address and class identifier to a replacement management table coupled to the range register. The replacement management table is configured to generate L2 tag replacement control indicia in response to a received requested address and class identifier. An L2 address register is coupled to the first address register and configured to request an address from an L2 cache. An L2 cache is coupled to the L2 address register and the replacement management table and is configured to determine whether a requested address is in the L2 cache and is further configured to assign replacement eligibility of at least one set of cache lines in the L2 cache in response to received L2 tag replacement control indicia. In response to a determination that a requested address is not in the L2 cache, the L2 cache is further configured to overwrite a cache line within a set of the L2 cache as a function of the replacement eligibility.
摘要翻译：本发明提供了一种用于管理高速缓存替换资格的系统。第一地址寄存器被配置为从L1高速缓存请求地址。 L1缓存被配置为确定所请求的地址是否在L1高速缓存中，并且响应于所请求的地址不在L1高速缓存中的确定，还被配置为将所请求的地址发送到耦合到L1的范围寄存器缓存。范围寄存器被配置为响应于接收到的请求的地址生成类标识符，并将所请求的地址和类标识符发送到耦合到范围寄存器的替换管理表。替换管理表被配置为响应于接收到的请求的地址和类标识符来生成L2标签替换控制标记。 L2地址寄存器耦合到第一地址寄存器并且被配置为从L2高速缓存请求地址。 L2缓存耦合到L2地址寄存器和替换管理表，并且被配置为确定所请求的地址是否在L2高速缓存中，并被进一步配置为在L2高速缓存中分配至少一组高速缓存行的替换资格响应接收的L2标签替换控制标记。响应于所请求的地址不在L2高速缓存中的确定，L2高速缓存进一步被配置为根据替换资格来覆盖L2高速缓存中的高速缓存行。

5. 发明授权

US07093080B2 Method and apparatus for coherent memory structure of heterogeneous processor systems 失效
标题翻译：异构处理器系统的相干存储器结构的方法和装置
公开(公告)号：US07093080B2
公开(公告)日：2006-08-15
申请号：US10682386
申请日：2003-10-09
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David J. Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David J. Shippy , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0835
摘要： Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.
摘要翻译：公开了与非均匀处理单元结合操作的一致的缓存系统。一组第一配置的处理单元具有常规高速缓存，并且通过使用常规MMU（存储器管理单元）直接访问公用或共享系统物理和虚拟地址存储器。需要访问系统存储器的不同配置和/或其他设备的其他处理器被配置为将访问的数据存储在兼容的高速缓存中。每个缓存与散列在高速缓存和系统存储器之间的给定协议相干存储器管理总线兼容。

6. 发明授权

US07200688B2 System and method asynchronous DMA command completion notification by accessing register via attached processing unit to determine progress of DMA command 有权
标题翻译：系统和方法异步DMA命令完成通过访问寄存器通过附加处理单元来确定DMA命令的进度
公开(公告)号：US07200688B2
公开(公告)日：2007-04-03
申请号：US10448237
申请日：2003-05-29
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , Peichum Peter Liu , Thuong Quang Truong , Takeshi Yamazaki
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , Peichum Peter Liu , Thuong Quang Truong , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides for asynchronous DMA command completion notification in a computer system. A command tag, associated with a plurality DMA command is generated. A DMA data movement command having the command tag is grouped with another DMA data movement command having the command tag. DMA commands belonging to the same tag group are monitored to see whether all DMA commands of the same tag group are completed.
摘要翻译：本发明在计算机系统中提供异步DMA命令完成通知。生成与多个DMA命令相关联的命令标签。具有命令标签的DMA数据移动命令与具有命令标签的另一DMA数据移动命令分组。监视属于同一标签组的DMA命令，以查看相同标签组的所有DMA命令是否完成。

7. 发明授权

US07546393B2 System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups 失效
标题翻译：用于异步DMA命令完成通知的系统，其中包括标签的DMA命令属于多个标签组
公开(公告)号：US07546393B2
公开(公告)日：2009-06-09
申请号：US11695436
申请日：2007-04-02
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , Peichum Peter Liu , Thuong Quang Truong , Takeshi Yamazaki
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , Peichum Peter Liu , Thuong Quang Truong , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.
摘要翻译：本发明提供一种包括配置成接收包括标签的DMA命令的DMA队列的系统，其中标签属于多个标签组之一。计数器耦合到DMA队列，并配置为在DMA队列接收到DMA命令时增加标签组所属标签组的标签组计数，并在执行DMA命令时递减标签组计数。标签组计数状态寄存器耦合到计数器，并被配置为存储多个标签组中的每一个的标签组计数。并且标签组计数状态寄存器被进一步配置为接收对标签组状态的请求并响应对标签组状态的请求。

8. 发明授权

US06820143B2 On-chip data transfer in multi-processor system 失效
标题翻译：多处理器系统中的片上数据传输
公开(公告)号：US06820143B2
公开(公告)日：2004-11-16
申请号：US10322127
申请日：2002-12-17
申请人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichun Peter Liu , David Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichun Peter Liu , David Shippy , Thuong Quang Truong
IPC分类号： G06F1328
CPC分类号： G06F12/0817 , G06F12/0897
摘要： A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.
摘要翻译：提供了一种通过在不同处理器之间提供直接数据传输来提高计算机系统的性能的系统和方法。该系统包括第一和第二处理器。第一个处理器需要数据。该系统还包括与第一处理器通信的目录。目录接收到数据的数据请求，并包含有关数据存储位置的信息。缓存耦合到第二处理器。当发现数据被存储在高速缓存中时，内部总线耦合在第一处理器和高速缓存之间以将数据从高速缓存传送到第一处理器。

9. 发明授权

US07721123B2 Method and apparatus for managing the power consumption of a data processing system 失效
标题翻译：用于管理数据处理系统的功耗的方法和装置
公开(公告)号：US07721123B2
公开(公告)日：2010-05-18
申请号：US12025649
申请日：2008-02-04
申请人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
发明人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F12/0831 , G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops
摘要翻译：基于微处理器的数据处理系统的一个组件，其包括用于调节可窥探组件中的功耗并具有门控存储器一致性属性的特征，被确定为处于相对不活动状态，并且转换到不可窥探的低功率模式。然后，当侦听请求发生时，响应于窥探请求发送重试协议。结合重试协议，发送信号使组件进入窥探模式。当请求重试监听时，组件处于全功率模式，并可以正常响应窥探请求。在snoop请求已满足后，组件再次进入低功耗模式。因此，该组件能够在两个snoops之间进入低功耗模式

10. 发明授权

US07114042B2 Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment 有权
标题翻译：在非对称异构多处理器环境中提供原子更新原语的方法
公开(公告)号：US07114042B2
公开(公告)日：2006-09-26
申请号：US10443727
申请日：2003-05-22
申请人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichum Peter Liu , Thuong Quang Truong
发明人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichum Peter Liu , Thuong Quang Truong
IPC分类号： G06F13/00
CPC分类号： G06F13/28 , G06F9/3004 , G06F9/30087 , G06F12/0831 , G06F2213/0038
摘要： The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.
摘要翻译：本发明提供了具有具有DMA传输的共享存储器的非对称单芯片异构多处理器计算机系统中的原子更新原语。从包括具有预留的get lock line命令，put lock line条件命令和put lock line无条件命令的集合中生成至少一个lock line命令。

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