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1. 发明授权

US08082423B2 Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates 失效
标题翻译：将清除矢量从第一执行单元直接生成到多个执行单元的每个其他执行单元，以便阻止所有寄存器更新
公开(公告)号：US08082423B2
公开(公告)日：2011-12-20
申请号：US11201683
申请日：2005-08-11
申请人： Christopher Michael Abernathy , Kurt Alan Feiste , David Scott Ray , David Shippy , Albert James Van Norstrand, Jr.
发明人： Christopher Michael Abernathy , Kurt Alan Feiste , David Scott Ray , David Shippy , Albert James Van Norstrand, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30123 , G06F9/3013 , G06F9/3859 , G06F9/3863 , G06F9/3885
摘要： A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a central collection point to re-distribute the flush signals to the execution units. Each unit generates a flush vector to all other execution units which is used to block register updates for the flushed instructions.
摘要翻译：提供了一种用于检测和处理微处理器系统中的指令齐平的方法和装置。提供了一种分布在数据处理系统中的所有执行单元的刷新机制。冲洗机构不需要中央收集点将刷新信号重新分配给执行单元。每个单元生成一个刷新向量到所有其他执行单元，用于阻止刷新指令的寄存器更新。

2. 发明授权

US07953960B2 Method and apparatus for delaying a load miss flush until issuing the dependent instruction 有权
标题翻译：用于延迟负载奇偶校验的方法和装置，直到发出依赖指令
公开(公告)号：US07953960B2
公开(公告)日：2011-05-31
申请号：US11252410
申请日：2005-10-18
申请人： Kurt Alan Feiste , David Scott Ray , David Shippy , Albert James Van Norstrand, Jr.
发明人： Kurt Alan Feiste , David Scott Ray , David Shippy , Albert James Van Norstrand, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3859 , G06F9/3861 , G06F9/3867
摘要： A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access instruction progresses down the pipeline and when the flush stage is reached, the processor checks the associated bit and flushes the register access instruction.
摘要翻译：流水线处理器具有在管线的发布阶段检测寄存器访问指令的存在的电路。在稍后阶段发生的负载丢失可能导致寄存器访问指令被标记有相关位。寄存器访问指令在流水线下进行，当达到flush阶段时，处理器检查相关的位并刷新寄存器访问指令。

3. 发明授权

US07313673B2 Fine grained multi-thread dispatch block mechanism 有权
标题翻译：细粒度多线程调度块机制
公开(公告)号：US07313673B2
公开(公告)日：2007-12-25
申请号：US11154158
申请日：2005-06-16
申请人： Christopher Michael Abernathy , Jonathan James Dement , Albert James Van Norstrand, Jr. , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James Dement , Albert James Van Norstrand, Jr. , David Shippy
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/3009 , G06F9/3802
摘要： The present invention provides a method, a computer program product, and an apparatus for blocking a thread at dispatch in a multi-thread processor for fine-grained control of thread performance. Multiple threads share a pipeline within a processor. Therefore, a long latency condition for an instruction on one thread can stall all of the threads that share the pipeline. A dispatch-block signaling instruction blocks the thread containing the long latency condition at dispatch. The length of the block matches the length of the latency, so the pipeline can dispatch instructions from the blocked thread after the long latency condition is resolved. In one embodiment the dispatch-block signaling instruction is a modified OR instruction and in another embodiment it is a Nop instruction. By blocking one thread at dispatch, the processor can dispatch instructions from the other threads during the block.
摘要翻译：本发明提供一种方法，计算机程序产品和用于在多线程处理器中调度线程的线程的装置，用于线程性能的细粒度控制。多个线程在处理器中共享流水线。因此，一个线程上的指令的长延迟条件可以阻止所有共享流水线的线程。调度块信令指令在发送时阻止包含长延迟条件的线程。块的长度与延迟的长度相匹配，因此，在长时间等待条件解决之后，流水线可以从阻塞的线程中分派指令。在一个实施例中，调度块信令指令是经修改的OR指令，在另一实施例中是Nop指令。通过在调度时阻止一个线程，处理器可以在块期间从其他线程分派指令。

4. 发明授权

US07370176B2 System and method for high frequency stall design 失效
标题翻译：高频失速设计系统及方法
公开(公告)号：US07370176B2
公开(公告)日：2008-05-06
申请号：US11204414
申请日：2005-08-16
申请人： Jonathan James DeMent , Kurt Alan Feiste , Robert Alan Philhower , David Shippy
发明人： Jonathan James DeMent , Kurt Alan Feiste , Robert Alan Philhower , David Shippy
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3875
摘要： A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.
摘要翻译：提出了一种用于高频失速设计的系统和方法。发行单元包括第一指令阶段，第二指令阶段和发布控制逻辑。在第一指令周期期间，发行单元执行两个任务，即1）位于第一指令阶段的指令移动到第二指令阶段，2）发行控制逻辑确定是否发出或停止指令基于其特定的指令属性和发布控制单元的先前状态，移动到第二指令阶段。在紧随第一指令周期的第二指令周期中，基于从第一指令周期的发布控制逻辑的判定，发出或停止第二指令级的指令。

5. 发明授权

US07350056B2 Method and apparatus for issuing instructions from an issue queue in an information handling system 失效
标题翻译：用于从信息处理系统中的发布队列发出指令的方法和装置
公开(公告)号：US07350056B2
公开(公告)日：2008-03-25
申请号：US11236838
申请日：2005-09-27
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Kurt Alan Feiste , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Kurt Alan Feiste , David Shippy
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3814 , G06F9/3838 , G06F9/3855
摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a matrix of storage cells configured in rows and columns including a first row that couples to execution units. Instructions advance toward issuance from row to row as unoccupied storage cells appear. Unoccupied cells appear when instructions advance toward the first row and upon issuance. When a particular row includes an instruction that is not ready-to-issue a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row may bypass the row including the stalled or not-ready-to-issue instruction. Out-of-order issuance of instructions to the execution units thus continues.
摘要翻译：信息处理系统包括处理器，其以程序顺序发出指令。处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。问题队列包括以行和列配置的存储单元矩阵，包括耦合到执行单元的第一行。显示从空行到无存储单元格时，逐行发行的说明。当指示向第一行发出时，出现未占用的单元格。当特定行包含一个尚未准备就绪的指令时，该指令发生停顿状态。然而，为了防止整个问题队列和处理器停止，另一行中的就绪指令可能绕过包括已停止或尚未就绪的指令的行。因此，对执行单元的指令的无序发布继续进行。

6. 发明申请

US20080148021A1 High Frequency Stall Design 审中-公开
标题翻译：高频失速设计
公开(公告)号：US20080148021A1
公开(公告)日：2008-06-19
申请号：US12036704
申请日：2008-02-25
申请人： Jonathan James DeMent , Kurt Alan Feiste , Robert Alan Philhower , David Shippy
发明人： Jonathan James DeMent , Kurt Alan Feiste , Robert Alan Philhower , David Shippy
IPC分类号： G06F9/312
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3875
摘要： An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.
摘要翻译：发行单元包括第一指令阶段，第二指令阶段和发布控制逻辑。在第一指令周期期间，发行单元执行两个任务，即1）位于第一指令阶段的指令移动到第二指令阶段，2）发行控制逻辑确定是否发出或停止指令基于其特定的指令属性和发布控制单元的先前状态，移动到第二指令阶段。在紧随第一指令周期的第二指令周期中，基于从第一指令周期的发布控制逻辑的判定，发出或停止第二指令级的指令。

7. 发明申请

US20080141014A1 LOAD ADDRESS DEPENDENCY MECHANISM SYSTEM AND METHOD IN A HIGH FREQUENCY, LOW POWER PROCESSOR SYSTEM 失效
标题翻译：低频处理器系统中的负载地址依赖机制和方法
公开(公告)号：US20080141014A1
公开(公告)日：2008-06-12
申请号：US12025658
申请日：2008-02-04
申请人： Brian David Barrick , Kimberly Marie Fensler , Dwain Alan Hicks , David Scott Ray , David Shippy , Takeki Osanai
发明人： Brian David Barrick , Kimberly Marie Fensler , Dwain Alan Hicks , David Scott Ray , David Shippy , Takeki Osanai
IPC分类号： G06F9/30
CPC分类号： G06F9/3834 , G06F9/3838
摘要： The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.
摘要翻译：本发明提供了一种用于高频，低功率处理器中的负载地址依赖机制的方法。接收对应于存储器地址的加载指令。识别与存储器地址相对应的至少一个未执行的先前指令。加载指令存储在缺省队列中。并且加载指令被标记为本地缺失。

8. 发明授权

US07769985B2 Load address dependency mechanism system and method in a high frequency, low power processor system 失效
标题翻译：在高频，低功耗处理器系统中加载地址依赖机制系统和方法
公开(公告)号：US07769985B2
公开(公告)日：2010-08-03
申请号：US12025658
申请日：2008-02-04
申请人： Brian David Barrick , Kimberly Marie Fernsler , Dwain Alan Hicks , David Scott Ray , David Shippy , Takeki Osanai
发明人： Brian David Barrick , Kimberly Marie Fernsler , Dwain Alan Hicks , David Scott Ray , David Shippy , Takeki Osanai
IPC分类号： G06F9/316
CPC分类号： G06F9/3834 , G06F9/3838
摘要： The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.
摘要翻译：本发明提供了一种用于高频，低功率处理器中的负载地址依赖机制的方法。接收对应于存储器地址的加载指令。识别与存储器地址相对应的至少一个未执行的先前指令。加载指令存储在未命中队列中。并且加载指令被标记为本地缺失。

9. 发明授权

US07363468B2 Load address dependency mechanism system and method in a high frequency, low power processor system 失效
标题翻译：在高频，低功耗处理器系统中加载地址依赖机制系统和方法
公开(公告)号：US07363468B2
公开(公告)日：2008-04-22
申请号：US10992381
申请日：2004-11-18
申请人： Brian David Barrick , Kimberly Marie Fensler , Dwain Alan Hicks , David Scott Ray , David Shippy , Takeki Osanai
发明人： Brian David Barrick , Kimberly Marie Fensler , Dwain Alan Hicks , David Scott Ray , David Shippy , Takeki Osanai
IPC分类号： G06F9/30
CPC分类号： G06F9/3834 , G06F9/3838
摘要： The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.
摘要翻译：本发明提供了一种用于高频，低功率处理器中的负载地址依赖机制的方法。接收对应于存储器地址的加载指令。识别与存储器地址相对应的至少一个未执行的先前指令。加载指令存储在未命中队列中。并且加载指令被标记为本地缺失。

10. 发明授权

US07913070B2 Time-of-life counter for handling instruction flushes from a queue 有权
标题翻译：处理指令的生命周期计数器从队列中刷新
公开(公告)号：US07913070B2
公开(公告)日：2011-03-22
申请号：US12250285
申请日：2008-10-13
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
IPC分类号： G06F7/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.
摘要翻译：介绍使用计数器跟踪发出的指令的顺序。在一个实施例中，使用饱和的递减计数器。计数器初始化为与处理器提交点对应的值。指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。一旦计数器达到零，将由执行单元完成。如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。

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