专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07313673B2 Fine grained multi-thread dispatch block mechanism 有权
标题翻译：细粒度多线程调度块机制
公开(公告)号：US07313673B2
公开(公告)日：2007-12-25
申请号：US11154158
申请日：2005-06-16
申请人： Christopher Michael Abernathy , Jonathan James Dement , Albert James Van Norstrand, Jr. , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James Dement , Albert James Van Norstrand, Jr. , David Shippy
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/3009 , G06F9/3802
摘要： The present invention provides a method, a computer program product, and an apparatus for blocking a thread at dispatch in a multi-thread processor for fine-grained control of thread performance. Multiple threads share a pipeline within a processor. Therefore, a long latency condition for an instruction on one thread can stall all of the threads that share the pipeline. A dispatch-block signaling instruction blocks the thread containing the long latency condition at dispatch. The length of the block matches the length of the latency, so the pipeline can dispatch instructions from the blocked thread after the long latency condition is resolved. In one embodiment the dispatch-block signaling instruction is a modified OR instruction and in another embodiment it is a Nop instruction. By blocking one thread at dispatch, the processor can dispatch instructions from the other threads during the block.
摘要翻译：本发明提供一种方法，计算机程序产品和用于在多线程处理器中调度线程的线程的装置，用于线程性能的细粒度控制。多个线程在处理器中共享流水线。因此，一个线程上的指令的长延迟条件可以阻止所有共享流水线的线程。调度块信令指令在发送时阻止包含长延迟条件的线程。块的长度与延迟的长度相匹配，因此，在长时间等待条件解决之后，流水线可以从阻塞的线程中分派指令。在一个实施例中，调度块信令指令是经修改的OR指令，在另一实施例中是Nop指令。通过在调度时阻止一个线程，处理器可以在块期间从其他线程分派指令。

2. 发明授权

US08028151B2 Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines 失效
标题翻译：通过不再需要跨不同执行管道的统一完成点来执行按顺序处理器的性能
公开(公告)号：US08028151B2
公开(公告)日：2011-09-27
申请号：US12277376
申请日：2008-11-25
申请人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
发明人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
IPC分类号： G06F9/30 , G06F9/00
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.
摘要翻译：一种用于改善按顺序处理器的性能的方法，系统和处理器。处理器可以包括具有包括备用流水线和常规流水线的执行流水线的执行单元。备用管道可以存储发给正常管道的指令的副本。执行流水线可以包括逻辑，用于在刷新比正常流水线中检测到的异常之后的指令更新时允许指令从备用流水线流向正常流水线。通过维护发布到常规流水线的指令的备份副本，可能不需要从单独的执行流程中刷新指令并重新获取。结果，可以将执行单元的结果完成到设计状态，从而使完成点在不同执行流水线之间变化。

3. 发明申请

US20090077352A1 PERFORMANCE OF AN IN-ORDER PROCESSOR BY NO LONGER REQUIRING A UNIFORM COMPLETION POINT ACROSS DIFFERENT EXECUTION PIPELINES 失效
标题翻译：不需要长时间执行订单处理器的性能，需要通过不同执行管道的均匀完成点
公开(公告)号：US20090077352A1
公开(公告)日：2009-03-19
申请号：US12277376
申请日：2008-11-25
申请人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
发明人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.
摘要翻译：一种用于改善按顺序处理器的性能的方法，系统和处理器。处理器可以包括具有包括备用流水线和常规流水线的执行流水线的执行单元。备用管道可以存储发给正常管道的指令的副本。执行流水线可以包括逻辑，用于在刷新比正常流水线中检测到的异常之后的指令更新时允许指令从备用流水线流向正常流水线。通过维护发布到常规流水线的指令的备份副本，可能不需要从单独的执行流程中刷新指令并重新获取。结果，可以将执行单元的结果完成到设计状态，从而使完成点在不同执行流水线之间变化。

4. 发明授权

US07475232B2 Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines 失效
标题翻译：通过不再需要跨不同执行管道的统一完成点来执行按顺序处理器的性能
公开(公告)号：US07475232B2
公开(公告)日：2009-01-06
申请号：US11184349
申请日：2005-07-19
申请人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
发明人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
IPC分类号： G06F9/00
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.
摘要翻译：一种用于改善按顺序处理器的性能的方法，系统和处理器。处理器可以包括具有包括备用流水线和常规流水线的执行流水线的执行单元。备用管道可以存储发给正常管道的指令的副本。执行流水线可以包括逻辑，用于在刷新比正常流水线中检测到的异常之后的指令更新时允许指令从备用流水线流向正常流水线。通过维护发布到常规流水线的指令的备份副本，可能不需要从单独的执行流程中刷新指令并重新获取。结果，可以将执行单元的结果完成到设计状态，从而使完成点在不同执行流水线之间变化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式