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1. 发明授权

US08244979B2 System and method for cache-locking mechanism using translation table attributes for replacement class ID determination 失效
标题翻译：用于缓存锁定机制的系统和方法使用转换表属性进行替换类ID确定
公开(公告)号：US08244979B2
公开(公告)日：2012-08-14
申请号：US11777331
申请日：2007-07-13
申请人： Adam Patrick Burns , Jason Nathaniel Dale , Jonathan James DeMent , Gavin Balfour Meil
发明人： Adam Patrick Burns , Jason Nathaniel Dale , Jonathan James DeMent , Gavin Balfour Meil
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/1036 , G06F12/1063
摘要： A system, method, and program product are provided that identifies a cache set using Translation LookAside Buffer (TLB) attributes. When a virtual address is requested, the method, system, and program product identifies a cache set using buffer attributes. When a virtual address is received, an attempt is made to load the received virtual address from a cache. When the attempt results in a cache miss, a page is identified within a Translation LookAside Buffer that includes the virtual address. A class identifier is then retrieved from the identified page, with the class identifier identifying a cache set that is selected from the cache.
摘要翻译：提供了使用Translation LookAside Buffer（TLB）属性来标识高速缓存集的系统，方法和程序产品。当请求虚拟地址时，方法，系统和程序产品使用缓冲区属性标识缓存集。当接收到虚拟地址时，尝试从高速缓存加载接收到的虚拟地址。当尝试导致高速缓存未命中时，在包括虚拟地址的翻译LookAside缓冲区内标识页面。然后从标识的页面检索类标识符，其中类标识符标识从高速缓存中选择的高速缓存集。

2. 发明授权

US08028151B2 Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines 失效
标题翻译：通过不再需要跨不同执行管道的统一完成点来执行按顺序处理器的性能
公开(公告)号：US08028151B2
公开(公告)日：2011-09-27
申请号：US12277376
申请日：2008-11-25
申请人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
发明人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
IPC分类号： G06F9/30 , G06F9/00
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.
摘要翻译：一种用于改善按顺序处理器的性能的方法，系统和处理器。处理器可以包括具有包括备用流水线和常规流水线的执行流水线的执行单元。备用管道可以存储发给正常管道的指令的副本。执行流水线可以包括逻辑，用于在刷新比正常流水线中检测到的异常之后的指令更新时允许指令从备用流水线流向正常流水线。通过维护发布到常规流水线的指令的备份副本，可能不需要从单独的执行流程中刷新指令并重新获取。结果，可以将执行单元的结果完成到设计状态，从而使完成点在不同执行流水线之间变化。

3. 发明授权

US07877550B2 Bus controller initiated write-through mechanism with hardware automatically generated clean command 有权
标题翻译：总线控制器启动直写机制，硬件自动生成清洁命令
公开(公告)号：US07877550B2
公开(公告)日：2011-01-25
申请号：US12273576
申请日：2008-11-19
申请人： Jonathan James DeMent , Kerey Michelle Tassin , Thuong Quang Truong
发明人： Jonathan James DeMent , Kerey Michelle Tassin , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0837 , G06F12/0831
摘要： A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previously loaded into the cache. A write-through command is sent to a system bus as a function of whether the address of the store data is valid. The bus controller is employed to sense the write-through command. If the write-through command is sensed, a clean command is generated by the bus controller. If the write-through command is sensed, the store data is written into the cache array, and the data is marked as modified. If the write-through command is sensed, the clean command is sent onto the system bus by the bus controller, thereby causing modified data to be written to memory.
摘要翻译：创建直写缓存方案。存储数据命令从处理单元发送到高速缓存阵列的高速缓存行。然后确定存储数据的地址是否有效，其中来自存储地址的原始数据已经被预先加载到高速缓存中。根据存储数据的地址是否有效，将一个直写命令发送到系统总线。总线控制器用于检测直写命令。如果感测到直写命令，则总线控制器产生清洁命令。如果检测到直写命令，则将存储数据写入高速缓存阵列，并将数据标记为修改。如果感测到直写命令，则清除命令由总线控制器发送到系统总线上，从而将修改的数据写入存储器。

4. 发明授权

US07370176B2 System and method for high frequency stall design 失效
标题翻译：高频失速设计系统及方法
公开(公告)号：US07370176B2
公开(公告)日：2008-05-06
申请号：US11204414
申请日：2005-08-16
申请人： Jonathan James DeMent , Kurt Alan Feiste , Robert Alan Philhower , David Shippy
发明人： Jonathan James DeMent , Kurt Alan Feiste , Robert Alan Philhower , David Shippy
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3875
摘要： A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.
摘要翻译：提出了一种用于高频失速设计的系统和方法。发行单元包括第一指令阶段，第二指令阶段和发布控制逻辑。在第一指令周期期间，发行单元执行两个任务，即1）位于第一指令阶段的指令移动到第二指令阶段，2）发行控制逻辑确定是否发出或停止指令基于其特定的指令属性和发布控制单元的先前状态，移动到第二指令阶段。在紧随第一指令周期的第二指令周期中，基于从第一指令周期的发布控制逻辑的判定，发出或停止第二指令级的指令。

5. 发明授权

US06967510B2 Time-base implementation for correcting accumulative error with chip frequency scaling 失效
公开(公告)号：US06967510B2
公开(公告)日：2005-11-22
申请号：US10687251
申请日：2003-10-16
申请人： Jonathan James DeMent , Rolf Hilgendorf , Cedric Lichtenau , Michael Fan Wang
发明人： Jonathan James DeMent , Rolf Hilgendorf , Cedric Lichtenau , Michael Fan Wang
IPC分类号： G06F1/14 , H03K19/00
CPC分类号： G06F1/14
摘要： The present invention provides for supporting an on chip-timer facility and, more particularly, to the generation of a constant time incremental increase while changing core mesh-clock frequency. A latch is coupled to the output of a first free-running clock. An inverter is coupled to the output of the first latch. At least one other secondary latch is coupled to the output of the first latch. An edge detector is coupled to the output of the secondary latch. An incrementer or decrementer is coupled to the output of the edge detector. A memory is coupled to the output of the incrementer or decrementer.

6. 发明授权

US07913070B2 Time-of-life counter for handling instruction flushes from a queue 有权
标题翻译：处理指令的生命周期计数器从队列中刷新
公开(公告)号：US07913070B2
公开(公告)日：2011-03-22
申请号：US12250285
申请日：2008-10-13
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
IPC分类号： G06F7/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.
摘要翻译：介绍使用计数器跟踪发出的指令的顺序。在一个实施例中，使用饱和的递减计数器。计数器初始化为与处理器提交点对应的值。指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。一旦计数器达到零，将由执行单元完成。如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。

7. 发明授权

US07831808B2 Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor 有权
标题翻译：队列设计系统支持通用处理器中的SIMD指令的依赖性检查和问题
公开(公告)号：US07831808B2
公开(公告)日：2010-11-09
申请号：US11961914
申请日：2007-12-20
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , David Shippy
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3859 , G06F9/3885 , G06F9/3887
摘要： A processor includes a general purpose (GP) unit adapted to receive and configured to execute GP instructions; and includes a single instruction multiple data (SIMD) unit adapted to receive and configured to execute SIMD instructions. An instruction unit comprises a first logic unit coupled to the GP unit and a second logic unit coupled to the SIMD unit, wherein SIMD instructions are processed subsequent to GP instructions. In the first logic unit a GP instruction with unresolved dependencies unconditionally causes subsequent SIMD instructions to stall, and an SIMD instruction with unresolved dependencies does not cause subsequent GP instructions to stall. The first logic unit resolves dependencies in GP instructions, provides dependency-free instructions to the GP unit, and provides SIMD instructions to the second logic unit. The second logic unit resolves dependencies in SIMD instructions and provides dependency-free instructions to the SIMD unit.
摘要翻译：处理器包括适于接收和配置为执行GP指令的通用（GP）单元; 并且包括适于接收和配置为执行SIMD指令的单指令多数据（SIMD）单元。指令单元包括耦合到GP单元的第一逻辑单元和耦合到SIMD单元的第二逻辑单元，其中在GP指令之后处理SIMD指令。在第一个逻辑单元中，具有未解决的依赖关系的GP指令无条件地导致后续的SIMD指令停止，并且具有未解决依赖性的SIMD指令不会导致后续的GP指令停止。第一个逻辑单元解决GP指令中的依赖关系，向GP单元提供无依赖指令，并向第二个逻辑单元提供SIMD指令。第二个逻辑单元解决SIMD指令中的依赖关系，并向SIMD单元提供无依赖指令。

8. 发明授权

US07516275B2 Pseudo-LRU virtual counter for a locking cache 失效
标题翻译：用于锁定缓存的伪LRU虚拟计数器
公开(公告)号：US07516275B2
公开(公告)日：2009-04-07
申请号：US11380140
申请日：2006-04-25
申请人： Jonathan James DeMent , Ronald P. Hall , Brian Patrick Hanley , Kevin C. Stelzer
发明人： Jonathan James DeMent , Ronald P. Hall , Brian Patrick Hanley , Kevin C. Stelzer
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/126 , G06F12/0842 , G06F12/124 , G06F12/125
摘要： A computer implemented method and system for managing replacement of sets in a locked cache. A cache access by a program is performed, and a side of a binary tree pointed to by a base leaf is identified. A determination is made as to whether a number of accesses to the identified side of the binary tree equals a number of sets associated with the program on the identified side. The base leaf is changed to point to an opposite side of the binary tree if the number of accesses to the identified side equals the number of sets associated with the program on the identified side.
摘要翻译：用于管理锁定高速缓存中的集合的替换的计算机实现的方法和系统。执行程序的高速缓存访问，并且识别由基本叶指向的二叉树的一侧。确定对二叉树的所识别侧的访问次数是否等于与所识别侧上的程序相关联的集合的数量。如果对所识别的边的访问次数等于与识别侧的程序相关联的集合的数目，则将基础叶改变为指向二叉树的相对侧。

9. 发明申请

US20090077323A1 Bus Controller Initiated Write-Through Mechanism with Hardware Automatically Generated Clean Command 有权
标题翻译：总线控制器启动的写入机制与硬件自动生成清洁命令
公开(公告)号：US20090077323A1
公开(公告)日：2009-03-19
申请号：US12273576
申请日：2008-11-19
申请人： Jonathan James DeMent , Kerey Michelle Tassin , Thuong Quang Truong
发明人： Jonathan James DeMent , Kerey Michelle Tassin , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0837 , G06F12/0831
摘要： A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previously loaded into the cache. A write-through command is sent to a system bus as a function of whether the address of the store data is valid. The bus controller is employed to sense the write-through command. If the write-through command is sensed, a clean command is generated by the bus controller. If the write-through command is sensed, the store data is written into the cache array, and the data is marked as modified. If the write-through command is sensed, the clean command is sent onto the system bus by the bus controller, thereby causing modified data to be written to memory.
摘要翻译：创建直写缓存方案。存储数据命令从处理单元发送到高速缓存阵列的高速缓存行。然后确定存储数据的地址是否有效，其中来自存储地址的原始数据已经被预先加载到高速缓存中。根据存储数据的地址是否有效，将一个直写命令发送到系统总线。总线控制器用于检测直写命令。如果感测到直写命令，则总线控制器产生清洁命令。如果检测到直写命令，则将存储数据写入高速缓存阵列，并将数据标记为修改。如果感测到直写命令，则清除命令由总线控制器发送到系统总线上，从而将修改的数据写入存储器。

10. 发明授权

US07490224B2 Time-of-life counter design for handling instruction flushes from a queue 失效
标题翻译：处理指令从队列刷新的生命周期计数器设计
公开(公告)号：US07490224B2
公开(公告)日：2009-02-10
申请号：US11246587
申请日：2005-10-07
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.
摘要翻译：介绍使用计数器跟踪发出的指令的顺序。在一个实施例中，使用饱和的递减计数器。计数器初始化为与处理器提交点对应的值。指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。一旦计数器达到零，将由执行单元完成。如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。

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