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1. 发明授权

US09137371B2 Leads processing engine 有权
标题翻译：引领加工引擎
公开(公告)号：US09137371B2
公开(公告)日：2015-09-15
申请号：US11774378
申请日：2007-07-06
申请人： Van Anderson , David H. Anderson , Brad L. Anderson , Michael B. Anderson , Jeffrey R. Anderson
发明人： Van Anderson , David H. Anderson , Brad L. Anderson , Michael B. Anderson , Jeffrey R. Anderson
IPC分类号： H04M3/00 , H04M5/00 , H04M3/523 , G06Q30/08
CPC分类号： G06Q10/063112 , G06Q30/08 , G06Q50/14 , H04M3/5233
摘要： The present invention is directed to a system and method for generating, processing and distributing leads, the system comprising a leads processing engine for receiving customer requests, creating leads based upon the customer requests, determining a best available agent or agents for each lead from a pool of available agents based upon one or more selected factors, and offering and/or sending each lead to the best available agent or agents.
摘要翻译：本发明涉及一种用于生成，处理和分发引线的系统和方法，该系统包括用于接收客户请求的引线处理引擎，基于客户请求创建引线，为每个引线确定最佳可用代理或代理基于一个或多个选择的因素的可用代理的池，以及提供和/或发送每个引导到最佳可用代理或代理。

2. 发明申请

US20100301923A1 MONOLITHIC VOLTAGE REFERENCE DEVICE WITH INTERNAL, MULTI-TEMPERATURE DRIFT DATA AND RELATED TESTING PROCEDURES 有权
标题翻译：具有内部，多温度数据和相关测试程序的单片电压参考设备
公开(公告)号：US20100301923A1
公开(公告)日：2010-12-02
申请号：US12475184
申请日：2009-05-29
申请人： Michael B. Anderson , Tahir M. Hasoon , Brendan J. Whelan , J. Spencer Wright , Robert L. Reay
发明人： Michael B. Anderson , Tahir M. Hasoon , Brendan J. Whelan , J. Spencer Wright , Robert L. Reay
IPC分类号： G01R19/00 , H01L35/00
CPC分类号： G01R31/2849 , G01R31/2874 , G01R35/007
摘要： A testing procedure may determine whether a monolithic voltage reference device meets a temperature drift specification. A first non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a first non-room temperature which is substantially different than room temperature. First non-room temperature information may be stored in a memory within the monolithic voltage reference device which is a function of the first non-room temperature output voltage. A second non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a second non-room temperature which is substantially different than the room temperature and the first non-room temperature. Second non-room temperature information may be stored in the memory without destroying the first non-room temperature information which is a function of the second non-room temperature output voltage. A determination may be made whether the monolithic voltage reference device meets the temperature drift specification based on a computation that is a function of both the first non-room temperature information and the second non-room temperature information.
摘要翻译：测试程序可以确定单片电压参考装置是否满足温度漂移规范。单片电压参考装置的第一非室温输出电压可以被测量，而单片电压参考装置处于与室温基本不同的第一非室温。第一非室温信息可以存储在作为第一非室温输出电压的函数的单片电压参考装置内的存储器中。单片电压参考装置的第二非室温输出电压可以被测量，而单片电压参考装置处于与室温和第一非室温基本上不同的第二非室温。可以将第二非室温信息存储在存储器中，而不破坏作为第二非室温输出电压的函数的第一非室温信息。可以基于作为第一非室内温度信息和第二非室内温度信息的函数的计算来确定单片电压参考装置是否满足温度漂移规格。

3. 发明授权

US07772920B1 Low thermal hysteresis bandgap voltage reference 有权
标题翻译：低热滞后带隙电压参考
公开(公告)号：US07772920B1
公开(公告)日：2010-08-10
申请号：US12474938
申请日：2009-05-29
申请人： Michael B. Anderson , Robert C. Dobkin , Brendan John Whelan
发明人： Michael B. Anderson , Robert C. Dobkin , Brendan John Whelan
IPC分类号： G06F1/10
CPC分类号： G05F3/30
摘要： A first and a second group of individual transistors in a voltage reference may collectively function as a first and a second composite transistor with a first and a second emitter area equal to the combined areas of the emitters of the first and the second groups of individual transistors, respectively. The second emitter area may be larger than the first emitter area. The stability of the reference voltage may depend upon the stability of the ratio between the first emitter area and the second emitter area. The first group of individual transistors may not be at the center of an arrangement of the second group of individual transistors. The constant reference voltage may vary due to thermal hysteresis by less than 200 parts per million over a 40 degree centigrade temperature range.
摘要翻译：电压基准中的第一组和第二组单独晶体管可共同用作第一和第二复合晶体管，其中第一和第二发射极面积等于第一和第二组单独晶体管的发射极的组合面积，分别。第二发射极区域可以大于第一发射极区域。参考电压的稳定性可以取决于第一发射极区域和第二发射极区域之间的比率的稳定性。第一组单独晶体管可能不在第二组单独晶体管的布置的中心。在40摄氏度的温度范围内，恒定的参考电压可能会因热滞后而小于200ppm。

4. 发明授权

US5953386A High speed clock recovery circuit using complimentary dividers 失效
标题翻译：高速时钟恢复电路使用免费分频器
公开(公告)号：US5953386A
公开(公告)日：1999-09-14
申请号：US667150
申请日：1996-06-20
申请人： Michael B. Anderson
发明人： Michael B. Anderson
IPC分类号： H03L3/00 , H03L7/087 , H03L7/089 , H04L7/033 , H03D3/24 , H03L7/06
CPC分类号： H03L7/0896 , H03L7/087 , H03L7/0891 , H04L7/033
摘要： A phase-locked loop circuit including a divider unit that receives a serial data stream at its input and generates a parallel data stream. The parallel data stream has a slower clock rate than the serial data stream according to the present invention. A phase detector unit has an input connected to the output of the divider unit for receiving the parallel data stream generated by the divider unit. The phase-locked loop circuit further includes a voltage controlled oscillator having an input connected to the output of the phase detector unit. The output of the voltage controlled oscillator is connected to another input of the phase detector, wherein the phase detector unit generates error signals that are sent to the voltage controlled oscillator.
摘要翻译：一种锁相环电路，包括在其输入端接收串行数据流并产生并行数据流的分频器单元。并行数据流具有比根据本发明的串行数据流更慢的时钟速率。相位检测器单元具有连接到除法器单元的输出的输入，用于接收由分频器单元产生的并行数据流。锁相环电路还包括具有连接到相位检测器单元的输出的输入端的压控振荡器。压控振荡器的输出端连接到相位检测器的另一个输入端，其中相位检测器单元产生发送到压控振荡器的误差信号。

5. 发明授权

US06285263B1 Linearization method and apparatus for voltage controlled oscillator 失效
标题翻译：压控振荡器的线性化方法和装置
公开(公告)号：US06285263B1
公开(公告)日：2001-09-04
申请号：US09063940
申请日：1998-04-21
申请人： Michael B. Anderson
发明人： Michael B. Anderson
IPC分类号： H03B502
CPC分类号： H03L7/0995 , H03B5/24 , H03B2201/02 , H03K3/0315 , H03K3/354
摘要： A voltage controlled oscillator (VCO) having a generally linear transfer characteristic across a wide frequency range of operation. The VCO is comprised of a voltage-to-current converter (V-I) and a current-controlled oscillator (ICO). A linearization of the output response of the VCO is accomplished by proper selection of the output responses of the V-I and ICO circuits, where the V-I portion is designed to have an inverse nonlinearity response as compared to the nonlinearity response of the ICO portion of the VCO. The combined effect is a linear response for the VCO. A nonlinear V-I characteristic can be achieved by adding several piecewise linear responses together to produce a combined nonlinear response.
摘要翻译：一种压控振荡器（VCO），其在宽的频率操作范围内具有大致线性的传递特性。 VCO由电压 - 电流转换器（V-I）和电流控制振荡器（ICO）组成。 VCO的输出响应的线性化通过对VI和ICO电路的输出响应的适当选择来实现，其中VI部分被设计为具有与VCO的ICO部分的非线性响应相比的反非线性响应。组合效应是VCO的线性响应。可以通过将多个分段线性响应加在一起以产生组合的非线性响应来实现非线性V-I特性。

6. 发明授权

US5987085A Clock recovery circuit 失效
标题翻译：时钟恢复电路
公开(公告)号：US5987085A
公开(公告)日：1999-11-16
申请号：US824170
申请日：1997-03-26
申请人： Michael B. Anderson
发明人： Michael B. Anderson
IPC分类号： H03L7/113 , H04L7/033 , H03D3/24
CPC分类号： H03L7/113 , H04L7/033
摘要： A phase locked loop, which does not require a local reference clock to obtain a frequency lock. The circuit includes a frequency locked loop and a phase locked loop in which the frequency locked loop does not require a local reference clock. The frequency locked loop includes a transition counter having an input for data with an output connected to a charge pump. This charge pump is connected to a loop filter, which in turn is connected to a voltage controlled oscillator. The output of the voltage controlled oscillator is connected to a second input in the transition counter. The phase locked loop includes a phase detector with an input for data. The output of this phase detector is connected to a second charge pump, which has it output connected to the loop filter. The output of the voltage controlled oscillator also is connected to the input of the phase detector.
摘要翻译：锁相环，不需要本地参考时钟来获得频率锁定。该电路包括频率锁定环和锁相环，锁相环不需要本地参考时钟。频率锁定环包括具有输出的转换计数器，其输出连接到电荷泵。该电荷泵连接到环路滤波器，环路滤波器又连接到压控振荡器。压控振荡器的输出端连接到转换计数器中的第二个输入端。锁相环包括具有数据输入的相位检测器。该相位检测器的输出端连接到第二个电荷泵，其输出端连接到环路滤波器。压控振荡器的输出也连接到相位检测器的输入端。

7. 发明授权

US5748050A Linearization method and apparatus for voltage controlled oscillator 失效
标题翻译：压控振荡器的线性化方法和装置
公开(公告)号：US5748050A
公开(公告)日：1998-05-05
申请号：US625452
申请日：1996-03-29
申请人： Michael B. Anderson
发明人： Michael B. Anderson
IPC分类号： H03B1/00 , H03B5/24 , H03K3/03 , H03K3/354 , H03L7/099 , H03B5/00
CPC分类号： H03L7/0995 , H03B5/24 , H03K3/0315 , H03K3/354 , H03B2201/02
摘要： A voltage controlled oscillator (VCO) having a generally linear transfer characteristic across a wide frequency range of operation. The VCO is comprised of a voltage-to-current converter (V-I) and a current-controlled oscillator (ICO). A linearization of the output response of the VCO is accomplished by proper selection of the output responses of the V-I and ICO circuits, where the V-I portion is designed to have an inverse nonlinearity response as compared to the nonlinearity response of the ICO portion of the VCO. The combined effect is a linear response for the VCO. A nonlinear V-I characteristic can be achieved by adding several piecewise linear responses together to produce a combined nonlinear response.
摘要翻译：一种压控振荡器（VCO），其在宽的频率操作范围内具有大致线性的传递特性。 VCO由电压 - 电流转换器（V-I）和电流控制振荡器（ICO）组成。 VCO的输出响应的线性化通过对VI和ICO电路的输出响应的适当选择来实现，其中VI部分被设计为具有与VCO的ICO部分的非线性响应相比的反非线性响应。组合效应是VCO的线性响应。可以通过将多个分段线性响应加在一起以产生组合的非线性响应来实现非线性V-I特性。

8. 发明授权

US5920211A Fully digital clock synthesizer 失效
标题翻译：全数字时钟合成器
公开(公告)号：US5920211A
公开(公告)日：1999-07-06
申请号：US825082
申请日：1997-03-27
申请人： Michael B. Anderson , Gregory A. Tabor
发明人： Michael B. Anderson , Gregory A. Tabor
IPC分类号： G06F11/36 , H03K5/00 , H03B19/00 , H03K3/017
CPC分类号： H03K5/00006
摘要： A fully digital clock multiplier capable of generating any N/M multiple of an input clock frequency with a precise duty cycle is provided. The input clock signal is divided by M to create a divided clock signal. The propagation of the input clock signal along a delay cell string during a half cycle of the divided clock signal is then measured. The measured propagation is then scaled by a factor N to select an appropriate delay cell string length within a ring oscillator for generating an output signal.
摘要翻译：提供了能够以精确占空比产生输入时钟频率的任何N / M倍数的全数字时钟倍增器。输入时钟信号被M除以产生分频时钟信号。然后测量在分频时钟信号的半周期期间沿着延迟单元串的输入时钟信号的传播。然后将测量的传播按因子N缩放以在环形振荡器内选择合适的延迟单元串长度以产生输出信号。

9. 发明授权

US5864246A Method and apparatus for doubling a clock signal using phase interpolation 失效
标题翻译：使用相位插值来加倍时钟信号的方法和装置
公开(公告)号：US5864246A
公开(公告)日：1999-01-26
申请号：US828496
申请日：1997-03-31
申请人： Michael B. Anderson
发明人： Michael B. Anderson
IPC分类号： H03B19/14 , H03K5/00 , H03B19/00
CPC分类号： H03B19/14 , H03K5/00006
摘要： A circuit for multiplying a clock signal. The circuit includes a phase interpolator having two inputs for receiving complementary clock signals. The output of the phase interpolator is connected to an input in an exclusive OR gate. One of the two complementary input signals also is sent into the exclusive OR gate, wherein a multiplied clock signal is generated at the output of the exclusive OR gate.
摘要翻译：用于乘以时钟信号的电路。该电路包括具有两个用于接收互补时钟信号的输入的相位插值器。相位内插器的输出连接到异或门中的输入。两个互补输入信号中的一个也被发送到异或门，其中在异或门的输出处产生相乘的时钟信号。

10. 发明授权

US5793822A Bist jitter tolerance measurement technique 失效
标题翻译：双边抖动容差测量技术
公开(公告)号：US5793822A
公开(公告)日：1998-08-11
申请号：US543767
申请日：1995-10-16
申请人： Michael B. Anderson , Philip A. Atkinson
发明人： Michael B. Anderson , Philip A. Atkinson
IPC分类号： H04L25/08 , H03L7/089 , H04B17/00 , H04L1/20 , H04L7/033 , H04L7/00
CPC分类号： H04L1/205 , H04B17/20 , H03L7/0896 , H04L7/033
摘要： A circuit in a semiconductor device for testing jitter tolerance of a receiver in the semiconductor device. The circuit includes a jitter injection circuit that has an output connected to an input in a phase-locked loop circuit. The jitter injection circuit generates an output signal in response to an application of an input signal. The phase-locked loop circuit has an output that generates a clock signal, wherein the clock signal may be altered by the output signal from the jitter injection circuit. The clock signal from the phase-locked loop circuit controls transmission of data at the transmitter. Alteration of the clock signal caused by the jitter injection circuit alters the manner in which the transmitter transmits data.
摘要翻译：半导体器件中用于测试半导体器件中的接收器的抖动容限的电路。电路包括抖动注入电路，其具有连接到锁相环电路中的输入的输出。抖动注入电路响应于输入信号的应用产生输出信号。锁相环电路具有产生时钟信号的输出，其中可以通过来自抖动注入电路的输出信号改变时钟信号。来自锁相环电路的时钟信号控制发射机的数据传输。由抖动注入电路引起的时钟信号的改变改变了发送器发送数据的方式。

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