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1. 发明授权

US06243784B1 Method and apparatus for providing precise circuit delays 有权
标题翻译：提供精确电路延迟的方法和装置
公开(公告)号：US06243784B1
公开(公告)日：2001-06-05
申请号：US09425493
申请日：1999-10-22
申请人： Michael B. Anderson , Gregory A. Tabor , Mark J. Jander
发明人： Michael B. Anderson , Gregory A. Tabor , Mark J. Jander
IPC分类号： H03H1126
CPC分类号： H03L7/0805 , H03K3/0315 , H03K5/133 , H03L7/0995
摘要： A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.
摘要翻译：精确的定时延迟方法和装置。与定时参考相结合的锁相环（PLL）用于校准精确的延迟。然后，这些延迟在整个芯片上复制并由与PLL中相同的电流控制。这使得延迟处理，电压和温度不敏感。可以通过多路复用器选择所需的延迟来编程延迟。提供高精度延迟对于诸如计算机总线隔离器的设备中使用是特别有利的。

2. 发明授权

US6115769A Method and apparatus for providing precise circuit delays 失效
标题翻译：提供精确电路延迟的方法和装置
公开(公告)号：US6115769A
公开(公告)日：2000-09-05
申请号：US672784
申请日：1996-06-28
申请人： Michael B. Anderson , Gregory A. Tabor , Mark J. Jander
发明人： Michael B. Anderson , Gregory A. Tabor , Mark J. Jander
IPC分类号： H03K3/03 , H03K5/13 , H03L7/099 , H03H11/26
CPC分类号： H03L7/0805 , H03K3/0315 , H03K5/133 , H03L7/0995
摘要： A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.
摘要翻译：精确的定时延迟方法和装置。与定时参考相结合的锁相环（PLL）用于校准精确的延迟。然后，这些延迟在整个芯片上复制并由与PLL中相同的电流控制。这使得延迟处理，电压和温度不敏感。可以通过多路复用器选择所需的延迟来编程延迟。提供高精度延迟对于诸如计算机总线隔离器的设备中使用是特别有利的。

3. 发明授权

US06441810B1 Telemetry encoding technique for smart stylus 失效
标题翻译：智能手写笔的遥测编码技术
公开(公告)号：US06441810B1
公开(公告)日：2002-08-27
申请号：US08551303
申请日：1995-10-31
申请人： Steven K. Skoog , Gregory A. Tabor
发明人： Steven K. Skoog , Gregory A. Tabor
IPC分类号： G09G500
CPC分类号： G06F3/0383 , G06F3/03545
摘要： The invention relates to the transmission of telemetry data from a stylus to a host computer via a serial, asynchronous data channel. The telemetry data is encoded into code-words using a specially selected error detecting or error correcting code, the code-words are transmitted from the stylus in a continuous, homogeneous data stream without the use of framing delimiters between adjacent code-words, and the code-words are then received by the host computer which separates the code-words according to the unique characteristics of the selected code. The code may be chosen based on both the error detection/correction requirements of the system and the probability that the code will create invalid intermediate code matches between consecutive back-to-back code-words. In one embodiment, the invention provides a synchronization scheme which greatly reduces the probability that invalid intermediate code matches will be recognized in the host computer as validly transmitted code-words.
摘要翻译：本发明涉及通过串行异步数据信道将遥测数据从手写笔传输到主计算机。使用专门选择的错误检测或纠错码将遥测数据编码为码字，不用在相邻码字之间使用帧定界符，从连续的均匀数据流中的手写笔传送码字，代码字然后由主计算机接收，主计算机根据所选代码的独特特性分离码字。可以基于系统的错误检测/校正要求以及代码将在连续的背对背代码字之间创建无效的中间代码匹配的概率来选择代码。在一个实施例中，本发明提供了一种同步方案，其大大降低了无效中间码匹配的可能性将在主计算机中被识别为有效传输的码字。

4. 发明授权

US5920211A Fully digital clock synthesizer 失效
标题翻译：全数字时钟合成器
公开(公告)号：US5920211A
公开(公告)日：1999-07-06
申请号：US825082
申请日：1997-03-27
申请人： Michael B. Anderson , Gregory A. Tabor
发明人： Michael B. Anderson , Gregory A. Tabor
IPC分类号： G06F11/36 , H03K5/00 , H03B19/00 , H03K3/017
CPC分类号： H03K5/00006
摘要： A fully digital clock multiplier capable of generating any N/M multiple of an input clock frequency with a precise duty cycle is provided. The input clock signal is divided by M to create a divided clock signal. The propagation of the input clock signal along a delay cell string during a half cycle of the divided clock signal is then measured. The measured propagation is then scaled by a factor N to select an appropriate delay cell string length within a ring oscillator for generating an output signal.
摘要翻译：提供了能够以精确占空比产生输入时钟频率的任何N / M倍数的全数字时钟倍增器。输入时钟信号被M除以产生分频时钟信号。然后测量在分频时钟信号的半周期期间沿着延迟单元串的输入时钟信号的传播。然后将测量的传播按因子N缩放以在环形振荡器内选择合适的延迟单元串长度以产生输出信号。

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