专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09059096B2 Method to form silicide contact in trenches 有权
标题翻译：在沟槽中形成硅化物接触的方法
公开(公告)号：US09059096B2
公开(公告)日：2015-06-16
申请号：US13356090
申请日：2012-01-23
申请人： Michael A. Guillorn , Christian Lavoie , Ghavam G. Shahidi , Bin Yang , Zhen Zhang
发明人： Michael A. Guillorn , Christian Lavoie , Ghavam G. Shahidi , Bin Yang , Zhen Zhang
IPC分类号： H01L23/62 , H01L21/285 , H01L21/8238 , H01L29/417 , H01L29/66 , H01L29/45 , H01L29/786 , H01L23/485 , H01L21/768
CPC分类号： H01L21/28518 , H01L21/76846 , H01L21/76855 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/41725 , H01L29/41733 , H01L29/41775 , H01L29/458 , H01L29/6659 , H01L29/66772 , H01L29/78621 , H01L2924/0002 , H01L2924/00
摘要： A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region.
摘要翻译：一种形成硅化物触点的方法包括在栅极间隔物，栅极叠层和第一半导体层上形成电介质层。第一半导体层包括源/漏区。在电介质层中形成接触沟槽，以暴露源/漏区域的至少一部分。在接触沟槽内形成第二半导体层。在第二半导体层上形成金属层。进行退火以在第二半导体层和金属层之间形成硅化物区域。在金属层或硅化物区域上形成导电接触层。

2. 发明申请

US20120302005A1 SELF ALIGNED CARBIDE SOURCE/DRAIN FET 有权
标题翻译：自对准碳源/漏极FET
公开(公告)号：US20120302005A1
公开(公告)日：2012-11-29
申请号：US13566050
申请日：2012-08-03
申请人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
发明人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
IPC分类号： H01L21/336 , B82Y40/00
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/16 , H01L29/1602 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.
摘要翻译：场效应晶体管包括金属碳化物源部分，金属碳化物漏极部分，将金属碳化物源部分与金属碳化物部分分离的绝缘碳部分，形成在绝缘和碳部分上的纳米结构，并将金属碳化物源部分连接到金属碳化物排出部分和形成在绝缘碳部分的至少一部分和至少一部分纳米结构上的栅堆叠。

3. 发明授权

US08841652B2 Self aligned carbide source/drain FET 有权
标题翻译：自对准碳化物源极/漏极FET
公开(公告)号：US08841652B2
公开(公告)日：2014-09-23
申请号：US12627120
申请日：2009-11-30
申请人： Cyril Cabral, Jr. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
发明人： Cyril Cabral, Jr. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
IPC分类号： H01L29/08 , H01L29/16 , H01L29/775 , B82Y10/00 , H01L51/10 , H01L51/00 , H01L51/05
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/16 , H01L29/1602 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.
摘要翻译：场效应晶体管包括金属碳化物源部分，金属碳化物漏极部分，将金属碳化物源部分与金属碳化物部分分离的绝缘碳部分，形成在绝缘和碳部分上的纳米结构，并将金属碳化物源部分连接到金属碳化物排出部分和形成在绝缘碳部分的至少一部分和至少一部分纳米结构上的栅堆叠。

4. 发明申请

US20110127493A1 SELF ALIGNED CARBIDE SOURCE/DRAIN FET 有权
标题翻译：自对准碳源/漏极FET
公开(公告)号：US20110127493A1
公开(公告)日：2011-06-02
申请号：US12627120
申请日：2009-11-30
申请人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
发明人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/16 , H01L29/1602 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.
摘要翻译：场效应晶体管包括金属碳化物源部分，金属碳化物漏极部分，将金属碳化物源部分与金属碳化物部分分离的绝缘碳部分，形成在绝缘和碳部分上的纳米结构，并将金属碳化物源部分连接到金属碳化物排出部分和形成在绝缘碳部分的至少一部分和至少一部分纳米结构上的栅堆叠。

5. 发明授权

US08658461B2 Self aligned carbide source/drain FET 有权
公开(公告)号：US08658461B2
公开(公告)日：2014-02-25
申请号：US13566050
申请日：2012-08-03
申请人： Cyril Cabral, Jr. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
发明人： Cyril Cabral, Jr. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
IPC分类号： H01L51/40
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/16 , H01L29/1602 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.

6. 发明申请

US20130020183A1 Silicide Micromechanical Device and Methods to Fabricate Same 有权
标题翻译：硅化物微机械装置及其制造方法
公开(公告)号：US20130020183A1
公开(公告)日：2013-01-24
申请号：US13625294
申请日：2012-09-24
申请人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
发明人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
IPC分类号： H01H59/00
CPC分类号： B81C1/00666 , B81C1/00952 , H01H1/0094 , H01H2001/0078
摘要： A miniaturized electro-mechanical switch includes a moveable portion having a contact configured to make, when the switch is actuated, an electrical connection between two stationary points. At least the contact is composed of a fully silicided material. A structure includes a silicon layer formed over an insulator layer and a micromechanical switch formed at least partially within the silicon layer. The micromechanical switch has a conductive structure, and where at least electrically contacting portions of the conductive structure are comprised of fully silicided material.
摘要翻译：小型化机电开关包括具有触点的可移动部分，该触点构造成当开关被致动时使得两个静止点之间的电连接。至少接触由完全硅化的材料组成。一种结构包括形成在绝缘体层上的硅层和至少部分地形成在硅层内的微机电开关。微机械开关具有导电结构，并且其中导电结构的至少电接触部分由完全硅化材料构成。

7. 发明申请

US20120318649A1 Silicide Micromechanical Device and Methods to Fabricate Same 有权
标题翻译：硅化物微机械装置及其制造方法
公开(公告)号：US20120318649A1
公开(公告)日：2012-12-20
申请号：US13164126
申请日：2011-06-20
申请人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
发明人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
IPC分类号： H01H57/00 , H01L21/285
CPC分类号： B81C1/00666 , B81C1/00952 , H01H1/0094 , H01H2001/0078
摘要： A method is disclosed to fabricate an electro-mechanical device such as a MEMS or NEMS switch. The method includes providing a silicon layer disposed over an insulating layer that is disposed on a silicon substrate; releasing a portion of the silicon layer from the insulating layer so that it is at least partially suspended over a cavity in the insulating layer; depositing a metal (e.g., Pt) on at least one surface of at least the released portion of the silicon layer and, using a thermal process, fully siliciding at least the released portion of the silicon layer using the deposited metal. The method eliminates silicide-induced stress to the released Si member, as the entire Si member is silicided. Furthermore no conventional wet chemical etch is used after forming the fully silicided material thereby reducing a possibility of causing corrosion of the silicide and an increase in stiction.
摘要翻译：公开了一种制造诸如MEMS或NEMS开关的机电装置的方法。该方法包括提供设置在设置在硅衬底上的绝缘层上的硅层; 从所述绝缘层释放所述硅层的一部分，使得其至少部分地悬挂在所述绝缘层中的空腔上; 在至少所述硅层的释放部分的至少一个表面上沉积金属（例如Pt），并且使用热处理，使用沉积的金属至少完全硅化硅层的释放部分。当整个Si元件被硅化时，该方法消除了对释放的Si元件的硅化物引起的应力。此外，在形成完全硅化材料之后，也不使用常规的湿化学蚀刻，从而减少引起硅化物腐蚀和粘性增加的可能性。

8. 发明授权

US09368502B2 Replacement gate multigate transistor for embedded DRAM 有权
标题翻译：用于嵌入式DRAM的替换门多栅极晶体管
公开(公告)号：US09368502B2
公开(公告)日：2016-06-14
申请号：US13274758
申请日：2011-10-17
申请人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Wilfried E. Haensch
发明人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Wilfried E. Haensch
IPC分类号： H01L27/108 , H01L21/02 , H01L21/84 , H01L29/78 , H01L29/49 , H01L29/66
CPC分类号： H01L27/10867 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10861 , H01L27/10876 , H01L27/10879 , H01L27/1207 , H01L29/0673 , H01L29/49 , H01L29/66545 , H01L29/785
摘要： A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
摘要翻译：存储器单元，存储器单元阵列，以及用于制造具有诸如完全耗尽的finFET或嵌入式DRAM中的纳米线晶体管等多重晶体管的存储单元的方法。存储单元包括沟槽电容器，非平面晶体管和将沟槽电容器电耦合到非平面晶体管的自对准硅化物互连。

9. 发明授权

US09214529B2 Fin Fet device with independent control gate 有权
标题翻译： Fin Fet设备具有独立的控制门
公开(公告)号：US09214529B2
公开(公告)日：2015-12-15
申请号：US13047132
申请日：2011-03-14
申请人： Josephine B. Chang , Michael A. Guillorn , Chung-hsun Lin
发明人： Josephine B. Chang , Michael A. Guillorn , Chung-hsun Lin
IPC分类号： H01L29/66 , H01L27/12 , H01L29/78 , B82Y10/00
CPC分类号： H01L29/66545 , B82Y10/00 , H01L27/1211 , H01L29/66795 , H01L29/7855
摘要： A FinFET device with an independent control gate, including: a silicon-on-insulator substrate; a non-planar multi-gate transistor disposed on the silicon-on-insulator substrate, the transistor comprising a conducting channel wrapped around a thin silicon fin; a source/drain extension region; an independently addressable control gate that is self-aligned to the fin and does not extend beyond the source/drain extension region, the control gate comprising: a thin layer of silicon nitride; and a plurality of spacers.
摘要翻译：一种具有独立控制栅极的FinFET器件，包括：绝缘体上硅衬底; 设置在绝缘体上硅衬底上的非平面多栅极晶体管，所述晶体管包括围绕薄硅片缠绕的导电沟道; 源极/漏极延伸区域; 独立可寻址的控制栅极，其与所述鳍片自对准并且不延伸超过所述源极/漏极延伸区域，所述控制栅极包括：氮化硅薄层; 和多个间隔件。

10. 发明授权

US08916054B2 High fidelity patterning employing a fluorohydrocarbon-containing polymer 有权
标题翻译：采用含氟代烃基聚合物的高保真图案
公开(公告)号：US08916054B2
公开(公告)日：2014-12-23
申请号：US13281749
申请日：2011-10-26
申请人： Markus Brink , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Hiroyuki Miyazoe , Masahiro Nakamura
发明人： Markus Brink , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Hiroyuki Miyazoe , Masahiro Nakamura
IPC分类号： B44C1/22 , H01L21/033 , H01L21/311 , G03F7/40 , G03F7/09
CPC分类号： G03F7/094 , G03F7/091 , G03F7/40 , H01L21/0332 , H01L21/31116 , H01L21/31122 , H01L21/31138 , H01L21/31144 , Y10T428/24479
摘要： A stack of a hard mask layer, a soft mask layer, and a photoresist is formed on a substrate. The photoresist is patterned to include at least one opening. The pattern is transferred into the soft mask layer by an anisotropic etch, which forms a carbon-rich polymer that includes more carbon than fluorine. The carbon-rich polymer can be formed by employing a fluorohydrocarbon-containing plasma generated with fluorohydrocarbon molecules including more hydrogen than fluorine. The carbon-rich polymer coats the sidewalls of the soft mask layer, and prevents widening of the pattern transferred into the soft mask. The photoresist is subsequently removed, and the pattern in the soft mask layer is transferred into the hard mask layer. Sidewalls of the hard mask layer are coated with the carbon-rich polymer to prevent widening of the pattern transferred into the hard mask.
摘要翻译：在基板上形成硬掩模层，软掩模层和光致抗蚀剂的堆叠。图案化光致抗蚀剂以包括至少一个开口。该图案通过各向异性蚀刻转移到软掩模层中，其形成包含比氟更多的碳的富碳聚合物。富含碳的聚合物可以通过使用包含比氟更多的氢的氟代烃分子产生的含氟代烃等离子体形成。富含碳的聚合物涂覆软掩模层的侧壁，并且防止转移到软掩模中的图案的加宽。随后去除光致抗蚀剂，并将软掩模层中的图案转移到硬掩模层中。用富含碳的聚合物涂覆硬掩模层的侧壁以防止转移到硬掩模中的图案变宽。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式