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1. 发明授权

US09368502B2 Replacement gate multigate transistor for embedded DRAM 有权
标题翻译：用于嵌入式DRAM的替换门多栅极晶体管
公开(公告)号：US09368502B2
公开(公告)日：2016-06-14
申请号：US13274758
申请日：2011-10-17
申请人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Wilfried E. Haensch
发明人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Wilfried E. Haensch
IPC分类号： H01L27/108 , H01L21/02 , H01L21/84 , H01L29/78 , H01L29/49 , H01L29/66
CPC分类号： H01L27/10867 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10861 , H01L27/10876 , H01L27/10879 , H01L27/1207 , H01L29/0673 , H01L29/49 , H01L29/66545 , H01L29/785
摘要： A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
摘要翻译：存储器单元，存储器单元阵列，以及用于制造具有诸如完全耗尽的finFET或嵌入式DRAM中的纳米线晶体管等多重晶体管的存储单元的方法。存储单元包括沟槽电容器，非平面晶体管和将沟槽电容器电耦合到非平面晶体管的自对准硅化物互连。

2. 发明申请

US20130092992A1 REPLACEMENT GATE MULTIGATE TRANSISTOR FOR EMBEDDED DRAM 有权
标题翻译：嵌入式DRAM的更换栅极多晶硅晶体管
公开(公告)号：US20130092992A1
公开(公告)日：2013-04-18
申请号：US13274758
申请日：2011-10-17
申请人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Wilfried E. Haensch
发明人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Wilfried E. Haensch
IPC分类号： H01L27/108 , H01L21/02 , B82Y99/00
CPC分类号： H01L27/10867 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10861 , H01L27/10876 , H01L27/10879 , H01L27/1207 , H01L29/0673 , H01L29/49 , H01L29/66545 , H01L29/785
摘要： A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
摘要翻译：存储器单元，存储器单元阵列，以及用于制造具有诸如完全耗尽的finFET或嵌入式DRAM中的纳米线晶体管等多重晶体管的存储单元的方法。存储单元包括沟槽电容器，非平面晶体管和将沟槽电容器电耦合到非平面晶体管的自对准硅化物互连。

3. 发明申请

US20130087882A1 LATERAL ETCH STOP FOR NEMS RELEASE ETCH FOR HIGH DENSITY NEMS/CMOS MONOLITHIC INTEGRATION 有权
公开(公告)号：US20130087882A1
公开(公告)日：2013-04-11
申请号：US13269552
申请日：2011-10-07
申请人： Josephine B. Chang , Leland Chang , Sebastian U. Engelmann , Michael A. Guillorn
发明人： Josephine B. Chang , Leland Chang , Sebastian U. Engelmann , Michael A. Guillorn
IPC分类号： H01L27/12 , H01L21/56
CPC分类号： B81C1/0023 , B81B2207/015 , B81C1/00801 , B81C2203/0714 , B81C2203/0742 , H01L21/565 , H01L21/845 , H01L27/1211 , H01L2924/0002 , H01L2924/00
摘要： Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS).

4. 发明授权

US09000556B2 Lateral etch stop for NEMS release etch for high density NEMS/CMOS monolithic integration 有权
公开(公告)号：US09000556B2
公开(公告)日：2015-04-07
申请号：US13269552
申请日：2011-10-07
申请人： Josephine B. Chang , Leland Chang , Sebastian U. Engelmann , Michael A. Guillorn
发明人： Josephine B. Chang , Leland Chang , Sebastian U. Engelmann , Michael A. Guillorn
IPC分类号： H01L21/70 , H01L21/84 , H01L27/12 , B81C1/00 , H01L21/56
CPC分类号： B81C1/0023 , B81B2207/015 , B81C1/00801 , B81C2203/0714 , B81C2203/0742 , H01L21/565 , H01L21/845 , H01L27/1211 , H01L2924/0002 , H01L2924/00
摘要： Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS).

5. 发明授权

US08432723B2 Nano-electro-mechanical DRAM cell 有权
标题翻译：纳电机电DRAM
公开(公告)号：US08432723B2
公开(公告)日：2013-04-30
申请号：US13015936
申请日：2011-01-28
申请人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Brian J. Li , Steven John Koester
发明人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Brian J. Li , Steven John Koester
IPC分类号： G11C11/24 , G11C5/00 , G11C5/06 , G11C11/34
CPC分类号： G11C11/404 , B82Y10/00 , G11C23/00 , H01L27/108 , H01L27/10861 , H01L28/82 , H01L28/86 , H01L29/0673 , H01L29/84 , Y10T29/4913
摘要： A DRAM cell and method for storing information in a dynamic random access memory using an electrostatic actuator beam to make an electrical connection between a storage capacitor and a bit line.
摘要翻译：一种用于使用静电致动器光束在动态随机存取存储器中存储信息以在存储电容器和位线之间形成电连接的DRAM单元和方法。

6. 发明申请

US20120195102A1 NANO-ELECTRO-MECHANICAL DRAM CELL 有权
标题翻译：纳米电子机械DRAM单元
公开(公告)号：US20120195102A1
公开(公告)日：2012-08-02
申请号：US13015936
申请日：2011-01-28
申请人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Brian J. Li , Steven John Koester
发明人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Brian J. Li , Steven John Koester
IPC分类号： G11C11/24 , H05K3/30
CPC分类号： G11C11/404 , B82Y10/00 , G11C23/00 , H01L27/108 , H01L27/10861 , H01L28/82 , H01L28/86 , H01L29/0673 , H01L29/84 , Y10T29/4913
摘要： A DRAM cell and method for storing information in a dynamic random access memory using an electrostatic actuator beam to make an electrical connection between a storage capacitor and a bit line.
摘要翻译：一种用于使用静电致动器光束在动态随机存取存储器中存储信息以在存储电容器和位线之间形成电连接的DRAM单元和方法。

7. 发明授权

US09214529B2 Fin Fet device with independent control gate 有权
标题翻译： Fin Fet设备具有独立的控制门
公开(公告)号：US09214529B2
公开(公告)日：2015-12-15
申请号：US13047132
申请日：2011-03-14
申请人： Josephine B. Chang , Michael A. Guillorn , Chung-hsun Lin
发明人： Josephine B. Chang , Michael A. Guillorn , Chung-hsun Lin
IPC分类号： H01L29/66 , H01L27/12 , H01L29/78 , B82Y10/00
CPC分类号： H01L29/66545 , B82Y10/00 , H01L27/1211 , H01L29/66795 , H01L29/7855
摘要： A FinFET device with an independent control gate, including: a silicon-on-insulator substrate; a non-planar multi-gate transistor disposed on the silicon-on-insulator substrate, the transistor comprising a conducting channel wrapped around a thin silicon fin; a source/drain extension region; an independently addressable control gate that is self-aligned to the fin and does not extend beyond the source/drain extension region, the control gate comprising: a thin layer of silicon nitride; and a plurality of spacers.
摘要翻译：一种具有独立控制栅极的FinFET器件，包括：绝缘体上硅衬底; 设置在绝缘体上硅衬底上的非平面多栅极晶体管，所述晶体管包括围绕薄硅片缠绕的导电沟道; 源极/漏极延伸区域; 独立可寻址的控制栅极，其与所述鳍片自对准并且不延伸超过所述源极/漏极延伸区域，所述控制栅极包括：氮化硅薄层; 和多个间隔件。

8. 发明授权

US08492748B2 Collapsable gate for deposited nanostructures 失效
标题翻译：用于沉积的纳米结构的可折叠门
公开(公告)号：US08492748B2
公开(公告)日：2013-07-23
申请号：US13169542
申请日：2011-06-27
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Philip S. Waggoner
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Philip S. Waggoner
IPC分类号： H01L29/06 , H01L31/00 , H01L29/15 , H01L51/40
CPC分类号： H01L29/66045 , H01L51/055
摘要： A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.
摘要翻译：一次性材料层首先沉积在石墨烯层或碳纳米管（CNT）上。一次性材料层包括比石墨烯或CNT更不惰性的材料，使得可以以目标电介质厚度沉积连续的电介质材料层而没有针孔。通过图案化连续的介电材料层和沉积在其上的栅极导体层来形成栅极叠层。一次性材料层在形成栅极叠层期间屏蔽并保护石墨烯层或CNT。然后通过选择性蚀刻去除一次性材料层，释放独立的栅极结构。独立栅极结构在选择性蚀刻结束时在石墨烯层或CNT上折叠，使得连续介电材料层的底表面接触石墨烯层或CNT的上表面。

9. 发明申请

US20120302005A1 SELF ALIGNED CARBIDE SOURCE/DRAIN FET 有权
标题翻译：自对准碳源/漏极FET
公开(公告)号：US20120302005A1
公开(公告)日：2012-11-29
申请号：US13566050
申请日：2012-08-03
申请人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
发明人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
IPC分类号： H01L21/336 , B82Y40/00
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/16 , H01L29/1602 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.
摘要翻译：场效应晶体管包括金属碳化物源部分，金属碳化物漏极部分，将金属碳化物源部分与金属碳化物部分分离的绝缘碳部分，形成在绝缘和碳部分上的纳米结构，并将金属碳化物源部分连接到金属碳化物排出部分和形成在绝缘碳部分的至少一部分和至少一部分纳米结构上的栅堆叠。

10. 发明授权

US07893492B2 Nanowire mesh device and method of fabricating same 有权
标题翻译：纳米线网装置及其制造方法
公开(公告)号：US07893492B2
公开(公告)日：2011-02-22
申请号：US12371943
申请日：2009-02-17
申请人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L21/02
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696 , Y10S977/72 , Y10S977/742 , Y10S977/762 , Y10S977/938
摘要： A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.
摘要翻译：提供一种半导体结构，其包括位于衬底表面上的多个垂直堆叠且垂直间隔开的半导体纳米线（例如，半导体纳米线网）。每个垂直堆叠和垂直间隔开的半导体纳米线的一个端段连接到源极区域，并且每个垂直堆叠和垂直间隔开的半导体纳米线的另一个端部段连接到漏极区域。包括栅极电介质和栅极导体的栅极区域邻接多个垂直堆叠和垂直间隔的半导体纳米线，并且源极区域和漏极区域与栅极区域自对准。

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