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1. 发明授权

US07085897B2 Memory management for a symmetric multiprocessor computer system 失效
标题翻译：对称多处理器计算机系统的内存管理
公开(公告)号：US07085897B2
公开(公告)日：2006-08-01
申请号：US10436491
申请日：2003-05-12
申请人： Michael A. Blake , Carl B. Ford , Pak-kin Mak , Gary E. Strait
发明人： Michael A. Blake , Carl B. Ford , Pak-kin Mak , Gary E. Strait
IPC分类号： G06F12/00
CPC分类号： G06F9/5016 , G06F12/0822
摘要： A modular multiprocessor computer system having a plurality of nodes each being in communication with each other via communication links. The plurality of nodes each have local memory and local cache accessible by the other nodes. The plurality of nodes each also having a cache directory, one or more processing units, and a memory coherent directory to keep track of the scope of ownership of data within the modular multiprocessing computer system. The local memory and the local cache contain configurable regions of storage, wherein memory coherency traffic on the communication links between the nodes is controlled through the use of the memory coherent directory during a data request.
摘要翻译：一种具有多个节点的模块化多处理器计算机系统，每个节点通过通信链路相互通信。多个节点各自具有本地存储器和由其他节点访问的本地高速缓存。多个节点每个还具有高速缓存目录，一个或多个处理单元和存储器相干目录，以跟踪模块化多处理计算机系统内的数据的所有权范围。本地存储器和本地高速缓存包含可配置的存储区域，其中在数据请求期间通过使用存储器相干目录来控制节点之间的通信链路上的存储器一致性流量。

2. 发明授权

US08656228B2 Memory error isolation and recovery in a multiprocessor computer system 有权
标题翻译：多处理器计算机系统中的内存错误隔离和恢复
公开(公告)号：US08656228B2
公开(公告)日：2014-02-18
申请号：US12821271
申请日：2010-06-23
申请人： Mark A. Check , David F. Craddock , Thomas A. Gregg , Pak-kin Mak , Gary E. Strait
发明人： Mark A. Check , David F. Craddock , Thomas A. Gregg , Pak-kin Mak , Gary E. Strait
IPC分类号： G06F11/00
CPC分类号： G06F11/0745 , G06F11/0724 , G06F11/0793 , G06F12/1458
摘要： A system and computer implemented method for isolating errors in a computer system is provided. The method includes receiving a direct memory access (DMA) command to access a computer memory, a read response, or an interrupt; associating the DMA command to access the computer memory, the read response, or the interrupt with a stream identified by a stream identification (ID); detecting a memory error caused by the DMA command in the stream, the memory error resulting in stale data in the computer memory; and isolating the memory error in the stream associated with the stream ID from other streams associated with other stream IDs upon detecting the memory error.
摘要翻译：提供了一种用于隔离计算机系统中的错误的系统和计算机实现的方法。该方法包括接收访问计算机存储器的直接存储器访问（DMA）命令，读取响应或中断; 将DMA命令与由流标识（ID）标识的流相关联以访问计算机存储器，读取响应或中断; 检测由流中的DMA命令引起的存储器错误，存储器错误导致计算机存储器中的过时数据; 并且在检测到存储器错误时，将与流ID相关联的流中的存储器错误与其他流ID相关联的其他流隔离。

3. 发明授权

US08250305B2 Method, system and computer program product for data buffers partitioned from a cache array 有权
标题翻译：从缓存阵列分区的数据缓冲区的方法，系统和计算机程序产品
公开(公告)号：US08250305B2
公开(公告)日：2012-08-21
申请号：US12051244
申请日：2008-03-19
申请人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
发明人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/126 , G06F2212/2515
摘要： Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.
摘要翻译：从缓存阵列分区的数据缓冲区的系统，方法和计算机程序产品。示例性实施例包括处理器中的方法并且用于提供从高速缓存阵列分区的数据缓冲器，该方法包括将与处理器相关联的高速缓存目录清除到初始状态，从由服务处理器预加载的控制寄存器获得所选择的目录状态，响应于包括所需缓存状态的控制寄存器，发送具有地址和数据的加载命令，将高速缓存行和高速缓存行目录条目加载到高速缓存中并将指定的数据存储在相应的高速缓存行中。

4. 发明申请

US20110320892A1 MEMORY ERROR ISOLATION AND RECOVERY IN A MULTIPROCESSOR COMPUTER SYSTEM 有权
标题翻译：多处理器计算机系统中的内存错误分离和恢复
公开(公告)号：US20110320892A1
公开(公告)日：2011-12-29
申请号：US12821271
申请日：2010-06-23
申请人： Mark A. Check , David F. Craddock , Thomas A. Gregg , Pak-kin Mak , Gary E. Strait
发明人： Mark A. Check , David F. Craddock , Thomas A. Gregg , Pak-kin Mak , Gary E. Strait
IPC分类号： G06F11/22 , G06F12/14 , G06F13/28
CPC分类号： G06F11/0745 , G06F11/0724 , G06F11/0793 , G06F12/1458
摘要： A system and computer implemented method for isolating errors in a computer system is provided. The method includes receiving a direct memory access (DMA) command to access a computer memory, a read response, or an interrupt; associating the DMA command to access the computer memory, the read response, or the interrupt with a stream identified by a stream identification (ID); detecting a memory error caused by the DMA command in the stream, the memory error resulting in stale data in the computer memory; and isolating the memory error in the stream associated with the stream ID from other streams associated with other stream IDs upon detecting the memory error.
摘要翻译：提供了一种用于隔离计算机系统中的错误的系统和计算机实现的方法。该方法包括接收访问计算机存储器的直接存储器访问（DMA）命令，读取响应或中断; 将DMA命令与由流标识（ID）标识的流相关联以访问计算机存储器，读取响应或中断; 检测由流中的DMA命令引起的存储器错误，存储器错误导致计算机存储器中的过时数据; 并且在检测到存储器错误时，将与流ID相关联的流中的存储器错误与其他流ID相关联的其他流隔离。

5. 发明申请

US20090240891A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DATA BUFFERS PARTITIONED FROM A CACHE ARRAY 有权
标题翻译：方法，系统和计算机程序产品用于从缓存区域分配的数据缓冲区
公开(公告)号：US20090240891A1
公开(公告)日：2009-09-24
申请号：US12051244
申请日：2008-03-19
申请人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
发明人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F2212/2515
摘要： Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.
摘要翻译：从缓存阵列分区的数据缓冲区的系统，方法和计算机程序产品。示例性实施例包括处理器中的方法并且用于提供从高速缓存阵列分区的数据缓冲器，该方法包括将与处理器相关联的高速缓存目录清除到初始状态，从由服务处理器预加载的控制寄存器获得所选择的目录状态，响应于包括所需缓存状态的控制寄存器，发送具有地址和数据的加载命令，将高速缓存行和高速缓存行目录条目加载到高速缓存中并将指定的数据存储在相应的高速缓存行中。

6. 发明授权

US07634708B2 Relocatable storage protect keys for system main memory 有权
标题翻译：系统主存储器的可重定位存储保护键
公开(公告)号：US07634708B2
公开(公告)日：2009-12-15
申请号：US11532294
申请日：2006-09-15
申请人： Kevin W. Kark , Liyong Wang , Carl B. Ford, III , Pak-kin Mak
发明人： Kevin W. Kark , Liyong Wang , Carl B. Ford, III , Pak-kin Mak
IPC分类号： G06F11/00
CPC分类号： G06F12/1475 , G06F11/08
摘要： Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can be fixed even though the physical location of the keys is relocated into a different region. A triple-detect double correct ECC scheme is used to protect keys. The ECC scheme is different from regular data in the storage and can be used to detect illegal access. Extra firmware and hardware is also designed to restrain customer's applications from directly accessing keys. With the key region being relocatable, the firmware could move the key region away from a known faulty area in a memory to improve system RAS. We also achieved the commonality objective that key memory device can use the same memory devices with other server systems that do not use keys.
摘要翻译：存储保护密钥和系统数据共享相同的物理存储。关键区域是通过固件动态重新定位。配置阵列用于将关键区域的绝对地址映射到其物理地址。即使键的物理位置被重新定位到不同的区域，键的绝对地址也可以被固定。三重检测双正确ECC方案用于保护密钥。 ECC方案与存储中的常规数据不同，可用于检测非法访问。额外的固件和硬件也旨在限制客户的应用程序直接访问密钥。在可重新定位关键区域的情况下，固件可以将密钥区域从存储器中的已知故障区域移开，以改善系统RAS。我们还实现了共同目标，即密钥存储设备可以与不使用密钥的其他服务器系统使用相同的存储设备。

7. 发明授权

US07590899B2 Processor memory array having memory macros for relocatable store protect keys 失效
标题翻译：处理器存储器阵列具有用于可重定位存储保护键的存储器宏
公开(公告)号：US07590899B2
公开(公告)日：2009-09-15
申请号：US11532267
申请日：2006-09-15
申请人： Donald J. Swietek , Bruce G. Hazelzet , Roger A. Rippens , Carl B. Ford, III , Kevin W. Kark , Pak-kin Mak , Liyong Wang
发明人： Donald J. Swietek , Bruce G. Hazelzet , Roger A. Rippens , Carl B. Ford, III , Kevin W. Kark , Pak-kin Mak , Liyong Wang
IPC分类号： G11C29/00 , G06F11/00 , G06F13/00
CPC分类号： G06F12/1416
摘要： A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and second ends having a width smaller than the length; a first plurality of connector locations on the first side extending along a first edge of the board that extends the length of the board, a second plurality of connector locations of the second side extending on the first edge of the board, a locating key having its center positioned on the first edge and located between 80 mm and 86 mm and optimized with a locating key 1.5 mm wide centered at 81.58 or 85.67 mm from the first end of the board and located between 64 and 70 mm and optimized with the locating key centered at 67.58 or 65.675 from the second end of the board. Each DIMM has memory regions comprising one of a plurality of physical entities hereafter referred to as memory macros which are relocatable regions which contain SP Keys and data set storage in the DIMM physical memory. These memory macros SP Key regions define an arbitrary logic structure for main storage which has a hard physical boundary.
摘要翻译：用于主机主存储子系统的DDR SDRAM DIMM具有在具有第一侧和第二侧的矩形印刷电路板上的多个DDR SDRAM，长度（152MM = 6英寸）在149和153毫米之间，并且在149.15mm处优化或151.35mm的长度，第一和第二端的宽度小于长度; 所述第一侧的第一多个连接器位置沿所述板的第一边缘延伸，所述第一边延伸所述板的长度，所述第二侧的第二多个连接器位置在所述板的第一边缘上延伸，定位键具有其中心位于第一个边缘，位于80 mm和86 mm之间，并使用1.5 mm宽的定位键进行优化，定位键距离板的第一端81.58或85.67 mm，位于64至70 mm之间，并以定位键为中心进行优化从板的第二端67.58或65.675。每个DIMM具有包括以下称为存储宏的多个物理实体中的一个的存储器区域，其是在DIMM物理存储器中包含SP密钥和数据集存储的可重定位区域。这些内存宏SP键区域为主存储器定义了一个具有硬物理边界的任意逻辑结构。

8. 发明申请

US20080072109A1 Processor memory array having memory macros for relocatable store protect keys 失效
标题翻译：处理器存储器阵列具有用于可重定位存储保护键的存储器宏
公开(公告)号：US20080072109A1
公开(公告)日：2008-03-20
申请号：US11532267
申请日：2006-09-15
申请人： Donald J. Swietek , Bruce G. Hazelzet , Roger A. Rippens , Carl B. Ford , Kevin W. Kark , Pak-kin Mak , Liyong Wang
发明人： Donald J. Swietek , Bruce G. Hazelzet , Roger A. Rippens , Carl B. Ford , Kevin W. Kark , Pak-kin Mak , Liyong Wang
IPC分类号： G06F12/16 , G06F11/07 , G06F11/22
CPC分类号： G06F12/1416
摘要： A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and second ends having a width smaller than the length; a first plurality of connector locations on the first side extending along a first edge of the board that extends the length of the board, a second plurality of connector locations of the second side extending on the first edge of the board, a locating key having its center positioned on the first edge and located between 80 mm and 86 mm and optimized with a locating key 1.5 mm wide centered at 81.58 or 85.67 mm from the first end of the board and located between 64 and 70 mm and optimized with the locating key centered at 67.58 or 65.675 from the second end of the board. Each DIMM has memory regions comprising one of a plurality of physical entities hereafter referred to as memory macros which are relocatable regions which contain SP Keys and data set storage in the DIMM physical memory. These memory macros SP Key regions define an arbitrary logic structure for main storage which has a hard physical boundary.
摘要翻译：用于主机主存储子系统的DDR SDRAM DIMM具有在具有第一侧和第二侧的矩形印刷电路板上的多个DDR SDRAM，长度（152MM = 6英寸）在149和153毫米之间，并且在149.15mm处优化或151.35mm的长度，第一和第二端的宽度小于长度; 所述第一侧的第一多个连接器位置沿所述板的第一边缘延伸，所述第一边延伸所述板的长度，所述第二侧的第二多个连接器位置在所述板的第一边缘上延伸，定位键具有其中心位于第一个边缘，位于80 mm和86 mm之间，并使用1.5 mm宽的定位键进行优化，定位键距离板的第一端81.58或85.67 mm，位于64至70 mm之间，并以定位键为中心进行优化从板的第二端67.58或65.675。每个DIMM具有包括以下称为存储宏的多个物理实体中的一个的存储器区域，其是在DIMM物理存储器中包含SP密钥和数据集存储的可重定位区域。这些内存宏SP键区域为主存储器定义了一个具有硬物理边界的任意逻辑结构。

9. 发明申请

US20080071964A1 Relocatable Storage Protect Keys for System Main Memory 有权
标题翻译：系统主存储器的可重新定位存储保护键
公开(公告)号：US20080071964A1
公开(公告)日：2008-03-20
申请号：US11532294
申请日：2006-09-15
申请人： Kevin W. Kark , Liyong Wang , Carl B. Ford , Pak-kin Mak
发明人： Kevin W. Kark , Liyong Wang , Carl B. Ford , Pak-kin Mak
IPC分类号： G06F12/14
CPC分类号： G06F12/1475 , G06F11/08
摘要： Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can be fixed even though the physical location of the keys is relocated into a different region. A triple-etect double correct ECC scheme is used to protect keys. The ECC scheme is different from regular data in the storage and can be used to detect illegal access. Extra firmware and hardware is also designed to restrain customer's applications from directly accessing keys. With the key region being relocatable, the firmware could move the key region away from a known faulty area in a memory to improve system RAS. We also achieved the commonality objective that key memory device can use the same memory devices with other server systems that do not use keys.
摘要翻译：存储保护密钥和系统数据共享相同的物理存储。关键区域是通过固件动态重新定位。配置阵列用于将关键区域的绝对地址映射到其物理地址。即使键的物理位置被重新定位到不同的区域，键的绝对地址也可以被固定。使用三重等效双重ECC方案来保护密钥。 ECC方案与存储中的常规数据不同，可用于检测非法访问。额外的固件和硬件也旨在限制客户的应用程序直接访问密钥。在可重新定位关键区域的情况下，固件可以将密钥区域从存储器中的已知故障区域移开，以改善系统RAS。我们还实现了共同目标，即密钥存储设备可以与不使用密钥的其他服务器系统使用相同的存储设备。

10. 发明授权

US06988173B2 Bus protocol for a switchless distributed shared memory computer system 失效
标题翻译：总线协议用于无交换分布式共享内存计算机系统
公开(公告)号：US06988173B2
公开(公告)日：2006-01-17
申请号：US10435878
申请日：2003-05-12
申请人： Michael A. Blake , Steven M. German , Pak-kin Mak , Adrian E. Seigler , Gary A. Van Huben
发明人： Michael A. Blake , Steven M. German , Pak-kin Mak , Adrian E. Seigler , Gary A. Van Huben
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system. The bus protocol also allows data to be returned on one of the two rings, with the ring selection determined by the relative placement of the source and destination nodes on each ring, in order to control latency and data bus utilization.
摘要翻译：公开了一种用于由多个节点组成的对称多处理计算机系统的总线协议，每个节点包含多个处理器，I / O设备，主存储器和包括具有顶级高速缓存的集成交换机的系统控制器。节点通过双同心环拓扑互连。总线协议用于以一种允许部分一致性结果与窥探请求和地址并行传送的方式来交换窥探请求和地址，数据，相关性信息和节点之间的操作状态，因为操作沿着每个环转发。每个节点将其自身的一致性结果与在将窥探请求转发之前接收的部分一致性结果相结合，将地址和更新的部分一致性结果合并到环上的下一个节点。该协议允许系统中的每个节点查看最终的一致性结果，而不需要请求节点将这些结果广播到系统中的所有其他节点。总线协议还允许在两个振铃中的一个上返回数据，其中环选择由每个振铃上的源节点和目的节点的相对位置确定，以便控制等待时间和数据总线的利用。

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