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1. 发明授权

US5692209A System resource conflict resolution apparatus 失效
标题翻译：系统资源冲突解决装置
公开(公告)号：US5692209A
公开(公告)日：1997-11-25
申请号：US484771
申请日：1995-06-07
申请人： Patrick J. Meaney , Adrian E. Seigler
发明人： Patrick J. Meaney , Adrian E. Seigler
IPC分类号： G06F12/06 , G06F1/32 , G06F9/38 , G06F9/46 , G06F9/50 , G06F12/16 , G06F13/18 , G06F15/00
CPC分类号： G06F9/5011 , G06F1/32 , G06F13/18 , G06F2209/507 , Y02B60/142
摘要： A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.
摘要翻译：一种系统资源使能装置，用于对包括代表资源当前和未来操作的寄存器的系统资源进行操作，模式生成器，将与所请求的资源操作相对应的模式应用于队列中的资源操作的多个请求中的每一个比较逻辑，如果请求将与其他资源操作冲突，则通过将应用于该请求的模式与该寄存器进行比较来确定多个请求中的每个请求，优先级授权逻辑如果没有确定冲突则向队列中的请求授予优先权并根据应用于请求的模式来更新寄存器，以及根据寄存器对资源进行操作的资源使能逻辑。

2. 发明授权

US4564944A Error correcting scheme 失效
标题翻译：纠错方案
公开(公告)号：US4564944A
公开(公告)日：1986-01-14
申请号：US567212
申请日：1983-12-30
申请人： Richard F. Arnold , John Cocke , Don Coppersmith , Adrian E. Seigler , Gary E. Strait
发明人： Richard F. Arnold , John Cocke , Don Coppersmith , Adrian E. Seigler , Gary E. Strait
IPC分类号： G06F11/10 , H03M13/00 , H03M13/05
CPC分类号： H03M13/05
摘要： A method and an apparatus are disclosed for converting error syndromes of an error-correcting code to pointers which identify the positions of the erroneous bits. Each syndrome is converted by a plurality of hashing functions into a plurality of hash words, which in turn are used to address a plurality of read-only stores. The outputs of the read-only stores are logically combined to obtain the respective error pointer. A preferred embodiment uses three hashing functions (41, 43, 45) and three read-only stores (53, 55, 57) and combines their outputs by an Exclusive-Or function (59). The storage capacity and the processing time required for syndrome-to-error pointer conversion are reduced by the disclosed scheme.
摘要翻译：公开了一种用于将错误校正码的误差综合变换为识别错误位的位置的指针的方法和装置。每个综合征由多个散列函数转换成多个散列字，这些散列字又用于寻址多个只读存储。只读存储器的输出逻辑组合以获得相应的错误指针。优选实施例使用三个散列函数（41,43,45）和三个只读存储器（53,55,57），并且通过异或函数（59）组合它们的输出。通过所公开的方案减少了对错误指针转换所需的存储容量和处理时间。

3. 发明申请

US20090183129A1 Method, System, and Program Product for Automated Verification of Gating Logic Using Formal Verification 有权
标题翻译：使用正式验证自动验证门控逻辑的方法，系统和程序产品
公开(公告)号：US20090183129A1
公开(公告)日：2009-07-16
申请号：US12139483
申请日：2008-06-15
申请人： Adrian E. Seigler , Gary A. Van Huben
发明人： Adrian E. Seigler , Gary A. Van Huben
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/504
摘要： Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.
摘要翻译：使用形式验证测试包含微电子器件的器件设计的门控规则。测试台设计代码是从包含硬件设计语言代码的设计源中为设备设计生成的。测试台设备代码上的正式验证过程确定设备设计中的设备是否在门控条件下稳定或不稳定。如果测试显示设计在门控条件下不稳定; 表明需要对设备设计进行硬件设计修复。如果没有，测试结束。

4. 发明申请

US20080276144A1 Method and System for Formal Verification of Partial Good Self Test Fencing Structures 有权
标题翻译：部分良好自检围栏结构的正式验证方法与系统
公开(公告)号：US20080276144A1
公开(公告)日：2008-11-06
申请号：US11744392
申请日：2007-05-04
申请人： Gary Van Huben , Adrian E. Seigler
发明人： Gary Van Huben , Adrian E. Seigler
IPC分类号： G01R31/3187
CPC分类号： G01R31/318385
摘要： The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested.
摘要翻译：将隔离逻辑应用于内置自检（BIST）硬件结构的目的是为了分离有缺陷的电路和利用剩余的良好电路的概念是芯片设计行业中众所周知的做法。这里描述的是一种用于验证部分防护逻辑的任何特定实施实际上提供了阻挡来自围栏界面的所有信号的下游影响的期望行为的方法，并且还确保部分防护不会无意中排除任何共同逻辑完全测试。

5. 发明授权

US07111130B2 Coherency management for a “switchless” distributed shared memory computer system 失效
公开(公告)号：US07111130B2
公开(公告)日：2006-09-19
申请号：US11402599
申请日：2006-04-12
申请人： Michael A. Blake , Pak-kin Mak , Adrian E. Seigler , Gary A. VanHuben
发明人： Michael A. Blake , Pak-kin Mak , Adrian E. Seigler , Gary A. VanHuben
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/0831
摘要： A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A receiver receives a plurality of incoming messages via the first or second ring and merges a plurality of incoming message responses with a local outgoing message response to provide a merged response. Each of the plurality of nodes includes any combination of the following: at least one processor, cache memory, a plurality of I/O adapters, and main memory. The system control element includes a plurality of controllers for maintaining coherency in the system.

6. 发明授权

US5710936A System resource conflict resolution method 失效
标题翻译：系统资源冲突解决方法
公开(公告)号：US5710936A
公开(公告)日：1998-01-20
申请号：US475672
申请日：1995-06-07
申请人： Patrick J. Meaney , Adrian E. Seigler
发明人： Patrick J. Meaney , Adrian E. Seigler
IPC分类号： G06F12/06 , G06F1/32 , G06F9/38 , G06F9/46 , G06F9/50 , G06F12/16 , G06F13/18 , G06F15/00
CPC分类号： G06F9/5011 , G06F1/32 , G06F13/18 , G06F2209/507 , Y02B60/142
摘要： A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.
摘要翻译：一种系统资源使能装置，用于对包括代表资源当前和未来操作的寄存器的系统资源进行操作，模式生成器，将与所请求的资源操作相对应的模式应用于队列中的资源操作的多个请求中的每一个比较逻辑，如果请求将与其他资源操作冲突，则通过将应用于该请求的模式与该寄存器进行比较来确定多个请求中的每个请求，优先级授权逻辑如果没有确定冲突则向队列中的请求授予优先权并根据应用于请求的模式来更新寄存器，以及根据寄存器对资源进行操作的资源使能逻辑。

7. 发明授权

US07971166B2 Method, system, and program product for automated verification of gating logic using formal verification 有权
标题翻译：使用形式验证自动验证门控逻辑的方法，系统和程序产品
公开(公告)号：US07971166B2
公开(公告)日：2011-06-28
申请号：US12139483
申请日：2008-06-15
申请人： Adrian E. Seigler , Gary A. Van Huben
发明人： Adrian E. Seigler , Gary A. Van Huben
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.
摘要翻译：使用形式验证测试包含微电子器件的器件设计的门控规则。测试台设计代码是从包含硬件设计语言代码的设计源中为设备设计生成的。测试台设备代码上的正式验证过程确定设备设计中的设备是否在门控条件下稳定或不稳定。如果测试显示设计在门控条件下不稳定; 表明需要对设备设计进行硬件设计修复。如果没有，测试结束。

8. 发明授权

US07448008B2 Method, system, and program product for automated verification of gating logic using formal verification 有权
标题翻译：使用形式验证自动验证门控逻辑的方法，系统和程序产品
公开(公告)号：US07448008B2
公开(公告)日：2008-11-04
申请号：US11468078
申请日：2006-08-29
申请人： Adrian E. Seigler , Gary A. Van Huben
发明人： Adrian E. Seigler , Gary A. Van Huben
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/504
摘要： Automated verification methodology parsing scripts auto generate testbench hardware design language, such as VHDL or Verilog, from the design source VHDL or Verilog. A formal verification model is then built comprising the testbench VHDL and the design under test. The resulting design verification tool then provides proofs and counterexamples for all of the rules, e.g., auto-generated rules, in the testbench.
摘要翻译：自动验证方法解析脚本从设计源VHDL或Verilog自动生成测试平台硬件设计语言，如VHDL或Verilog。然后构建一个正式的验证模型，包括测试台VHDL和被测设计。因此，所产生的设计验证工具将为测试平台中的所有规则（例如自动生成的规则）提供证明和反例。

9. 发明授权

US07085898B2 Coherency management for a “switchless” distributed shared memory computer system 失效
标题翻译： “无切换”分布式共享内存计算机系统的一致性管理
公开(公告)号：US07085898B2
公开(公告)日：2006-08-01
申请号：US10435776
申请日：2003-05-12
申请人： Michael A. Blake , Pak-kin Mak , Adrian E. Seigler , Gary A. VanHuben
发明人： Michael A. Blake , Pak-kin Mak , Adrian E. Seigler , Gary A. VanHuben
IPC分类号： G06F12/00 , G06F15/167 , H04L12/43
CPC分类号： G06F12/0813 , G06F12/0831
摘要： An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O adapters, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. Local controllers on any given node initiate bus operations on behalf of said processors and I/O adapters on that node. Snoop requests are launched onto the ring topology simultaneously in both directions. As the messages traverse the nodes on the ring, they trigger remote controllers to perform coherent actions such as cache accesses or directory updates. Messages arriving on each node from both directions are combined with each other and with locally generated responses to form cumulative final responses. Additionally, controllers on the requesting node may perform local coherent actions based on the information conveyed by the returning final responses. Overall system coherency is maintained through the use of a dual token based scheme which provide coherency points to permit multiple non-contending requests for the same data unit. The cache coherency methods described herein further ensure the latest copy of data is always accessed or modified even when multiple copies are present throughout the multi-nodal system structure. Traditional cache management states are extended to include Intervention Master and Multiple Copy status which minimize overall bus utilization. A novel ring protocol is contemplated which efficiently packages coherency information into bus operational responses that also allow simultaneous data transfers in the direction of minimal latency.
摘要翻译：公开了一种用于管理具有多个节点的对称多处理环境中的存储一致性的装置和方法，每个节点包含多个处理器，I / O适配器，主存储器和包括具有顶级缓存的集成开关的系统控制器。节点通过双同心环拓扑互连。任何给定节点上的本地控制器代表该节点上的所述处理器和I / O适配器启动总线操作。 Snoop请求在两个方向同时发送到环形拓扑上。当消息遍历环上的节点时，它们触发远程控制器执行诸如缓存访问或目录更新之类的一致操作。从两个方向到达每个节点的消息彼此组合并且具有本地生成的响应以形成累积的最终响应。此外，请求节点上的控制器可以基于返回的最终响应传达的信息来执行本地一致的动作。通过使用基于双令牌的方案来维护总体系统一致性，其提供相干点以允许对相同数据单元的多个非竞争请求。本文所述的高速缓存一致性方法进一步确保即使在整个多节点系统结构中存在多个副本，始终访问或修改数据的最新副本。传统的缓存管理状态被扩展到包括干预主机和复制状态，从而最大限度地减少总线总线利用率。考虑了一种新颖的环路协议，其有效地将一致性信息包装到总线操作响应中，其也允许以最小延迟的方向同时进行数据传输。

10. 发明授权

US07661050B2 Method and system for formal verification of partial good self test fencing structures 有权
标题翻译：部分良好自检围栏结构的形式验证方法和系统
公开(公告)号：US07661050B2
公开(公告)日：2010-02-09
申请号：US11744392
申请日：2007-05-04
申请人： Gary Van Huben , Adrian E. Seigler
发明人： Gary Van Huben , Adrian E. Seigler
IPC分类号： G01R31/3187 , G01R31/40
CPC分类号： G01R31/318385
摘要： The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested.
摘要翻译：将隔离逻辑应用于内置自检（BIST）硬件结构的目的是为了分离有缺陷的电路和利用剩余的良好电路的概念是芯片设计行业中众所周知的做法。这里描述的是一种用于验证部分防护逻辑的任何特定实施实际上提供了阻挡来自围栏界面的所有信号的下游影响的期望行为的方法，并且还确保部分防护不会无意中排除任何共同逻辑完全测试。

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