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1. 发明申请

US20090240891A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DATA BUFFERS PARTITIONED FROM A CACHE ARRAY 有权
标题翻译：方法，系统和计算机程序产品用于从缓存区域分配的数据缓冲区
公开(公告)号：US20090240891A1
公开(公告)日：2009-09-24
申请号：US12051244
申请日：2008-03-19
申请人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
发明人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F2212/2515
摘要： Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.
摘要翻译：从缓存阵列分区的数据缓冲区的系统，方法和计算机程序产品。示例性实施例包括处理器中的方法并且用于提供从高速缓存阵列分区的数据缓冲器，该方法包括将与处理器相关联的高速缓存目录清除到初始状态，从由服务处理器预加载的控制寄存器获得所选择的目录状态，响应于包括所需缓存状态的控制寄存器，发送具有地址和数据的加载命令，将高速缓存行和高速缓存行目录条目加载到高速缓存中并将指定的数据存储在相应的高速缓存行中。

2. 发明授权

US08250305B2 Method, system and computer program product for data buffers partitioned from a cache array 有权
标题翻译：从缓存阵列分区的数据缓冲区的方法，系统和计算机程序产品
公开(公告)号：US08250305B2
公开(公告)日：2012-08-21
申请号：US12051244
申请日：2008-03-19
申请人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
发明人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/126 , G06F2212/2515
摘要： Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.
摘要翻译：从缓存阵列分区的数据缓冲区的系统，方法和计算机程序产品。示例性实施例包括处理器中的方法并且用于提供从高速缓存阵列分区的数据缓冲器，该方法包括将与处理器相关联的高速缓存目录清除到初始状态，从由服务处理器预加载的控制寄存器获得所选择的目录状态，响应于包括所需缓存状态的控制寄存器，发送具有地址和数据的加载命令，将高速缓存行和高速缓存行目录条目加载到高速缓存中并将指定的数据存储在相应的高速缓存行中。

3. 发明授权

US07779189B2 Method, system, and computer program product for pipeline arbitration 失效
标题翻译：管道仲裁的方法，系统和计算机程序产品
公开(公告)号：US07779189B2
公开(公告)日：2010-08-17
申请号：US12035249
申请日：2008-02-21
申请人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
发明人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
IPC分类号： G06F13/36 , G06F12/00 , G06F13/00 , H03M13/00
CPC分类号： G06F13/36
摘要： A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.
摘要翻译：一种用于流水线仲裁的方法，包括从第一流水线接收对共享芯片接口的第一请求，确定第一请求是否需要共享芯片接口的响应总线，以及如果确定不需要响应总线第一请求，认为第一请求仅需要共享芯片接口的地址总线，对从第二管道接收的用于访问地址总线的共享芯片接口的第二请求仲裁第一请求，将第一请求发送到所述地址总线如果所述第一请求通过所述第二请求获胜所述仲裁，并且如果所述第二请求通过所述第一请求获胜仲裁，则拒绝所述第一请求。相应的系统和计算机程序产品。

4. 发明申请

US20090216933A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PIPELINE ARBITRATION 失效
标题翻译：用于管道仲裁的方法，系统和计算机程序产品
公开(公告)号：US20090216933A1
公开(公告)日：2009-08-27
申请号：US12035249
申请日：2008-02-21
申请人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
发明人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.
摘要翻译：一种用于流水线仲裁的方法，包括从第一流水线接收对共享芯片接口的第一请求，确定第一请求是否需要共享芯片接口的响应总线，以及如果确定不需要响应总线第一请求，认为第一请求仅需要共享芯片接口的地址总线，对从第二管道接收的用于访问地址总线的共享芯片接口的第二请求仲裁第一请求，将第一请求发送到所述地址总线如果所述第一请求通过所述第二请求获胜所述仲裁，并且如果所述第二请求通过所述第一请求获胜仲裁，则拒绝所述第一请求。相应的系统和计算机程序产品。

5. 发明申请

US20090216955A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR LRU COMPARTMENT CAPTURE 有权
标题翻译：方法，系统和计算机程序产品用于LRU间隔捕获
公开(公告)号：US20090216955A1
公开(公告)日：2009-08-27
申请号：US12035906
申请日：2008-02-22
申请人： Arthur J. O'Neill, JR. , Michael F. Fee , Pak-kin Mak
发明人： Arthur J. O'Neill, JR. , Michael F. Fee , Pak-kin Mak
IPC分类号： G06F12/00
CPC分类号： G06F12/123 , G06F12/0859
摘要： A two pipe pass method for least recently used (LRU) compartment capture in a multiprocessor system. The method includes receiving a fetch request via a requesting processor and accessing a cache directory based on the received fetch request, performing a first pipe pass by determining whether a fetch hit or a fetch miss has occurred in the cache directory, and determining an LRU compartment associated with a specified congruence class of the cache directory based on the fetch request received, when it is determined that a fetch miss has occurred, and performing a second pipe pass by using the LRU compartment determined and the specified congruence class to access the cache directory and to select an LRU address to be cast out of the cache directory.
摘要翻译：在多处理器系统中用于最近最少使用（LRU）隔室捕获的两个管道通过方法。该方法包括：通过请求处理器接收提取请求，并基于接收的提取请求访问高速缓存目录;通过确定高速缓存目录中是否发生了提取命中或提取丢失，执行第一管道通路，以及确定LRU隔间当确定已经发生提取未命中时，基于所接收的获取请求与缓存目录的指定同余类相关联，并且通过使用确定的LRU隔离区和指定的一致等级来访问高速缓存目录来执行第二管道传递并选择要从缓存目录中抛出的LRU地址。

6. 发明申请

US20110320755A1 TRACKING DYNAMIC MEMORY REALLOCATION USING A SINGLE STORAGE ADDRESS CONFIGURATION TABLE 失效
标题翻译：使用单个存储地址配置表跟踪动态内存重新安装
公开(公告)号：US20110320755A1
公开(公告)日：2011-12-29
申请号：US12821986
申请日：2010-06-23
申请人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
发明人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
IPC分类号： G06F12/06
CPC分类号： G06F12/0292
摘要： Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table.
摘要翻译：使用具有第一寄存器和第二寄存器的单个配置表来跟踪动态存储器去分配包括将第一寄存器设置为活动寄存器，启动从存储器分区的期望存储增量的去分配，在第二寄存器中设置存储增量注册为无效，清除与单个配置表相关联的所有高速缓存，将第二个寄存器设置为活动寄存器，将第一个寄存器设置为非活动寄存器，将第一个寄存器中的所需存储增量设置为无效，将活动寄存器从第二个注册到第一个寄存器，使用单个配置表完成内存取消分配。

7. 发明授权

US08645642B2 Tracking dynamic memory reallocation using a single storage address configuration table 失效
标题翻译：使用单个存储地址配置表跟踪动态内存重新分配
公开(公告)号：US08645642B2
公开(公告)日：2014-02-04
申请号：US12821986
申请日：2010-06-23
申请人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
发明人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
IPC分类号： G06F12/00
CPC分类号： G06F12/0292
摘要： Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table.
摘要翻译：使用具有第一寄存器和第二寄存器的单个配置表来跟踪动态存储器去分配包括将第一寄存器设置为活动寄存器，启动从存储器分区的期望存储增量的去分配，在第二寄存器中设置存储增量注册为无效，清除与单个配置表相关联的所有高速缓存，将第二个寄存器设置为活动寄存器，将第一个寄存器设置为非活动寄存器，将第一个寄存器中的所需存储增量设置为无效，将活动寄存器从第二个注册到第一个寄存器，使用单个配置表完成内存取消分配。

8. 发明授权

US08180970B2 Least recently used (LRU) compartment capture in a cache memory system 有权
标题翻译：在缓存存储器系统中最近使用的（LRU）隔离区
公开(公告)号：US08180970B2
公开(公告)日：2012-05-15
申请号：US12035906
申请日：2008-02-22
申请人： Arthur J. O'Neill, Jr. , Michael F. Fee , Pak-kin Mak
发明人： Arthur J. O'Neill, Jr. , Michael F. Fee , Pak-kin Mak
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/123 , G06F12/0859
摘要： A two pipe pass method for least recently used (LRU) compartment capture in a multiprocessor system. The method includes receiving a fetch request via a requesting processor and accessing a cache directory based on the received fetch request, performing a first pipe pass by determining whether a fetch hit or a fetch miss has occurred in the cache directory, and determining an LRU compartment associated with a specified congruence class of the cache directory based on the fetch request received, when it is determined that a fetch miss has occurred, and performing a second pipe pass by using the LRU compartment determined and the specified congruence class to access the cache directory and to select an LRU address to be cast out of the cache directory.
摘要翻译：在多处理器系统中用于最近最少使用（LRU）隔室捕获的两个管道通过方法。该方法包括：通过请求处理器接收提取请求，并基于接收的提取请求访问高速缓存目录;通过确定高速缓存目录中是否发生了提取命中或提取丢失，执行第一管道通路，以及确定LRU隔间当确定已经发生提取未命中时，基于所接收的获取请求与缓存目录的指定同余类相关联，并且通过使用确定的LRU隔离区和指定的一致等级来访问高速缓存目录来执行第二管道传递并选择要从缓存目录中抛出的LRU地址。

9. 发明授权

US08635409B2 Dynamic mode transitions for cache instructions 失效
标题翻译：高速缓存指令的动态模式转换
公开(公告)号：US08635409B2
公开(公告)日：2014-01-21
申请号：US12821706
申请日：2010-06-23
申请人： Deanna Postles Dunn Berger , Michael F. Fee , Kenneth D. Klapproth , Robert J. Sonnelitter, III
发明人： Deanna Postles Dunn Berger , Michael F. Fee , Kenneth D. Klapproth , Robert J. Sonnelitter, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0855 , G06F12/0811 , G06F12/084 , G06F12/0846
摘要： A method of providing requests to a cache pipeline includes receiving a plurality of requests from one or more state machines at an arbiter; selecting one of the plurality of requests as a selected request the selected request having been provided by a first state machine; determining that the selected request includes a mode that requires a first step and a second step, the first step including an access to a location in a cache; determining that the location in the cache is unavailable; and replacing the mode with a modified mode that only includes the second step.
摘要翻译：向缓存流水线提供请求的方法包括：从仲裁器的一个或多个状态机接收多个请求; 从所选择的请求中选择所述多个请求中的一个请求，所述请求已由第一状态机提供; 确定所选择的请求包括需要第一步骤和第二步骤的模式，所述第一步骤包括对高速缓存中的位置的访问; 确定高速缓存中的位置不可用; 并用仅包括第二步的修改模式替换该模式。

10. 发明授权

US08407420B2 System, apparatus and method utilizing early access to shared cache pipeline for latency reduction 失效
标题翻译：利用早期访问共享缓存流水线进行延迟降低的系统，装置和方法
公开(公告)号：US08407420B2
公开(公告)日：2013-03-26
申请号：US12821721
申请日：2010-06-23
申请人： Deanna Postles Dunn Berger , Michael F. Fee , Robert J. Sonnelitter, III
发明人： Deanna Postles Dunn Berger , Michael F. Fee , Robert J. Sonnelitter, III
IPC分类号： G06F13/00 , G06F12/08
CPC分类号： G06F12/0857 , G06F12/084
摘要： A memory system, apparatus and method for performing operations in a shared cache coupled to a first requester and a second requester. The method includes receiving at the shared cache a first request from the second requester; assigning the request to a state machine; transmitting a first pipe pass request from the state machine to an arbiter; providing a first instruction from the first pipe pass request to a cache pipeline, the first instruction causing a first pipe pass; and providing a second pipe pass request to the arbiter before the first pipe pass is completed. The first requester may be a lower level cache such as an L2 cache, or an I/O device and the second requester may be an upper level cache such as an L4 cache, and the first request may be a coherency request.
摘要翻译：一种用于在耦合到第一请求者和第二请求者的共享高速缓存中执行操作的存储器系统，装置和方法。该方法包括在共享缓存中接收来自第二请求者的第一请求; 将请求分配给状态机; 将来自状态机的第一管道通过请求发送到仲裁器; 提供从所述第一管道通过请求到高速缓存流水线的第一指令，所述第一指令引起第一管道通过; 以及在第一管道通过完成之前向仲裁者提供第二管道通过请求。第一请求者可以是诸如L2高速缓存或I / O设备的低级缓存，并且第二请求者可以是诸如L4高速缓存的上级高速缓存，并且第一请求可以是一致性请求。

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