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1. 发明授权

US07060627B2 Method of decreasing charging effects in oxide-nitride-oxide (ONO) memory arrays 失效
标题翻译：降低氧化物 - 氧化物（ONO）存储器阵列中的充电效应的方法
公开(公告)号：US07060627B2
公开(公告)日：2006-06-13
申请号：US10659042
申请日：2003-09-09
申请人： Micha Gutman , Yakov Roizin , Menachem Vofsy , Efraim Aloni , Avi Ben-Gigi , Fumihiko Noro , Masatoshi Arai , Nobuyoshi Takahashi , Koji Yoshida
发明人： Micha Gutman , Yakov Roizin , Menachem Vofsy , Efraim Aloni , Avi Ben-Gigi , Fumihiko Noro , Masatoshi Arai , Nobuyoshi Takahashi , Koji Yoshida
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833
摘要： A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.
摘要翻译：无场阵列包括半导体衬底，形成在半导体衬底的上表面上的多个氧化物 - 氮化物氧化物（ONO）结构，以及形成在ONO结构上的多个字线，其中每个ONO结构基本上被一条字线覆盖。字线（通常为多晶硅）在随后的处理步骤期间阻挡UV照射，从而基本上防止电子被捕获在ONO结构的氮化硅层中。结果，无栅阵列晶体管的阈值电压随着无栅阵列晶体管的宽度减小而不会严重增加。

2. 发明申请

US20050054161A1 Method of decreasing charging effects in oxide-nitride-oxide (ONO) memory arrays 失效
标题翻译：降低氧化物 - 氧化物（ONO）存储器阵列中的充电效应的方法
公开(公告)号：US20050054161A1
公开(公告)日：2005-03-10
申请号：US10659042
申请日：2003-09-09
申请人： Micha Gutman , Yakov Roizin , Menachem Vofsy , Efraim Aloni , Avi Ben-Gigi , Fumihiko Noro , Masatoshi Arai , Nobuyoshi Takahashi , Koji Yoshida
发明人： Micha Gutman , Yakov Roizin , Menachem Vofsy , Efraim Aloni , Avi Ben-Gigi , Fumihiko Noro , Masatoshi Arai , Nobuyoshi Takahashi , Koji Yoshida
IPC分类号： H01L21/336 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833
摘要： A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.
摘要翻译：无场阵列包括半导体衬底，形成在半导体衬底的上表面上的多个氧化物 - 氮化物氧化物（ONO）结构，以及形成在ONO结构上的多个字线，其中每个ONO结构基本上被一条字线覆盖。字线（通常为多晶硅）在随后的处理步骤期间阻挡UV照射，从而基本上防止电子被捕获在ONO结构的氮化硅层中。结果，无栅阵列晶体管的阈值电压随着无栅阵列晶体管的宽度减小而不会严重增加。

3. 发明申请

US20060035418A1 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20060035418A1
公开(公告)日：2006-02-16
申请号：US11187958
申请日：2005-07-25
申请人： Koji Yoshida , Keita Takahashi , Fumihiko Noro , Masatoshi Arai , Nobuyoshi Takahashi
发明人： Koji Yoshida , Keita Takahashi , Fumihiko Noro , Masatoshi Arai , Nobuyoshi Takahashi
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L27/115 , H01L27/11568
摘要： First, on a semiconductor region of a first conductivity type, a trapping film is formed which stores information by accumulating charges. Then, the trapping film is formed with a plurality of openings, and impurity ions of a second conductivity type are implanted into the semiconductor region from the formed openings, thereby forming a plurality of diffused layers of the second conductivity type in portions of the semiconductor region located below the openings, respectively. An insulating film is formed to cover edges of the trapping film located toward the openings, and then the semiconductor region is subjected to a thermal process in an atmosphere containing oxygen to oxidize upper portions of the diffused layers. Thereby, insulating oxide films are formed in the upper portions of the diffused layers, respectively. Subsequently, a conductive film is formed over the trapping film including the edges thereof to form an electrode.
摘要翻译：首先，在第一导电类型的半导体区域上，形成通过累积电荷来存储信息的捕获膜。然后，捕获膜形成有多个开口，并且第二导电类型的杂质离子从形成的开口注入到半导体区域中，从而在半导体区域的部分中形成多个第二导电类型的扩散层分别位于开口下方。形成绝缘膜以覆盖位于开口的捕获膜的边缘，然后在含氧气氛中对半导体区域进行热处理，以氧化扩散层的上部。因此，绝缘氧化膜分别形成在扩散层的上部。随后，在包括其边缘的捕获膜上形成导电膜以形成电极。

4. 发明授权

US07951679B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07951679B2
公开(公告)日：2011-05-31
申请号：US11187958
申请日：2005-07-25
申请人： Koji Yoshida , Keita Takahashi , Fumihiko Noro , Masatoshi Arai , Nobuyoshi Takahashi
发明人： Koji Yoshida , Keita Takahashi , Fumihiko Noro , Masatoshi Arai , Nobuyoshi Takahashi
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： First, on a semiconductor region of a first conductivity type, a trapping film is formed which stores information by accumulating charges. Then, the trapping film is formed with a plurality of openings, and impurity ions of a second conductivity type are implanted into the semiconductor region from the formed openings, thereby forming a plurality of diffused layers of the second conductivity type in portions of the semiconductor region located below the openings, respectively. An insulating film is formed to cover edges of the trapping film located toward the openings, and then the semiconductor region is subjected to a thermal process in an atmosphere containing oxygen to oxidize upper portions of the diffused layers. Thereby, insulating oxide films are formed in the upper portions of the diffused layers, respectively. Subsequently, a conductive film is formed over the trapping film including the edges thereof to form an electrode.
摘要翻译：首先，在第一导电类型的半导体区域上，形成通过累积电荷来存储信息的捕获膜。然后，捕获膜形成有多个开口，并且第二导电类型的杂质离子从形成的开口注入到半导体区域中，从而在半导体区域的部分中形成多个第二导电类型的扩散层分别位于开口下方。形成绝缘膜以覆盖位于开口的捕获膜的边缘，然后在含氧气氛中对半导体区域进行热处理，以氧化扩散层的上部。因此，绝缘氧化膜分别形成在扩散层的上部。随后，在包括其边缘的捕获膜上形成导电膜以形成电极。

5. 发明申请

US20060086971A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060086971A1
公开(公告)日：2006-04-27
申请号：US11152114
申请日：2005-06-15
申请人： Nobuyoshi Takahashi , Satoshi Iwamoto , Fumihiko Noro , Masatoshi Arai
发明人： Nobuyoshi Takahashi , Satoshi Iwamoto , Fumihiko Noro , Masatoshi Arai
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/823878 , H01L27/105 , H01L27/1052 , H01L27/11573 , H01L29/792 , Y10S438/954
摘要： A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.
摘要翻译：一种半导体器件包括形成在半导体衬底上的存储器部分，并且包括具有可存储半导体衬底和存储电极之间的电荷的ONO膜的第一晶体管和用于隔离第一晶体管的第一STI区域和形成在半导体衬底并且包括具有CMOS电极和栅极电介质的第二晶体管和用于隔离第二晶体管的第二STI区域。第一STI区域的顶表面的高度被设定为等于或小于第二STI区域的顶表面的高度。

6. 发明授权

US07598589B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07598589B2
公开(公告)日：2009-10-06
申请号：US11152114
申请日：2005-06-15
申请人： Nobuyoshi Takahashi , Satoshi Iwamoto , Fumihiko Noro , Masatoshi Arai
发明人： Nobuyoshi Takahashi , Satoshi Iwamoto , Fumihiko Noro , Masatoshi Arai
IPC分类号： H01L27/105
CPC分类号： H01L27/11568 , H01L21/823878 , H01L27/105 , H01L27/1052 , H01L27/11573 , H01L29/792 , Y10S438/954
摘要： A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.
摘要翻译：一种半导体器件包括形成在半导体衬底上的存储器部分，并且包括具有可存储半导体衬底和存储电极之间的电荷的ONO膜的第一晶体管和用于隔离第一晶体管的第一STI区域和形成在半导体衬底并且包括具有CMOS电极和栅极电介质的第二晶体管和用于隔离第二晶体管的第二STI区域。第一STI区域的顶表面的高度被设定为等于或小于第二STI区域的顶表面的高度。

7. 发明授权

US07781291B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07781291B2
公开(公告)日：2010-08-24
申请号：US12551848
申请日：2009-09-01
申请人： Nobuyoshi Takahashi , Satoshi Iwamoto , Fumihiko Noro , Masatoshi Arai
发明人： Nobuyoshi Takahashi , Satoshi Iwamoto , Fumihiko Noro , Masatoshi Arai
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/823878 , H01L27/105 , H01L27/1052 , H01L27/11573 , H01L29/792 , Y10S438/954
摘要： A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.
摘要翻译：一种半导体器件包括形成在半导体衬底上的存储器部分，并且包括具有可存储半导体衬底和存储电极之间的电荷的ONO膜的第一晶体管和用于隔离第一晶体管的第一STI区域和形成在半导体衬底并且包括具有CMOS电极和栅极电介质的第二晶体管和用于隔离第二晶体管的第二STI区域。第一STI区域的顶表面的高度被设定为等于或小于第二STI区域的顶表面的高度。

8. 发明申请

US20080048247A1 Semiconductor device and semiconductor device fabrication method 有权
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20080048247A1
公开(公告)日：2008-02-28
申请号：US11806887
申请日：2007-06-05
申请人： Koji Yoshida , Masataka Kusumi , Hiroaki Kuriyama , Fumihiko Noro , Nobuyoshi Takahashi
发明人： Koji Yoshida , Masataka Kusumi , Hiroaki Kuriyama , Fumihiko Noro , Nobuyoshi Takahashi
IPC分类号： H01L29/792 , H01L21/336 , H01L21/4763
CPC分类号： H01L29/792 , H01L21/0217 , H01L21/02211 , H01L21/02222 , H01L21/02271 , H01L21/02337 , H01L21/28282 , H01L21/3125 , H01L21/3185 , H01L21/76834 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/511 , H01L29/7923
摘要： A semiconductor device includes: source/drain regions formed in a semiconductor substrate; a trapping film for storing information by accumulating charges, the trapping film being formed in a region on the semiconductor substrate which includes a region on a channel region between the source/drain regions; and gate electrodes formed on the trapping film. A silicon nitride film containing carbon is formed by low pressure CVD using an organic material so as to cover the gate electrodes and a part of the trapping film which is located between adjacent gate electrodes.
摘要翻译：半导体器件包括：形成在半导体衬底中的源/漏区; 用于通过累积电荷来存储信息的捕集膜，所述捕获膜形成在所述半导体衬底上的包括所述源极/漏极区之间的沟道区域上的区域的区域中; 以及形成在捕获膜上的栅电极。通过使用有机材料的低压CVD形成含有碳的氮化硅膜，以覆盖位于相邻栅电极之间的栅电极和捕获膜的一部分。

9. 发明授权

US07807557B2 Method of forming a semiconductor device having a trapping film for charge accumulation 有权
标题翻译：形成具有用于电荷累积的捕获膜的半导体器件的方法
公开(公告)号：US07807557B2
公开(公告)日：2010-10-05
申请号：US11806887
申请日：2007-06-05
申请人： Koji Yoshida , Masataka Kusumi , Hiroaki Kuriyama , Fumihiko Noro , Nobuyoshi Takahashi
发明人： Koji Yoshida , Masataka Kusumi , Hiroaki Kuriyama , Fumihiko Noro , Nobuyoshi Takahashi
IPC分类号： H01L21/76
CPC分类号： H01L29/792 , H01L21/0217 , H01L21/02211 , H01L21/02222 , H01L21/02271 , H01L21/02337 , H01L21/28282 , H01L21/3125 , H01L21/3185 , H01L21/76834 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/511 , H01L29/7923
摘要： A semiconductor device includes: source/drain regions formed in a semiconductor substrate; a trapping film for storing information by accumulating charges, the trapping film being formed in a region on the semiconductor substrate which includes a region on a channel region between the source/drain regions; and gate electrodes formed on the trapping film. A silicon nitride film containing carbon is formed by low pressure CVD using an organic material so as to cover the gate electrodes and a part of the trapping film which is located between adjacent gate electrodes.
摘要翻译：半导体器件包括：形成在半导体衬底中的源/漏区; 用于通过累积电荷来存储信息的捕集膜，所述捕获膜形成在所述半导体衬底上的包括所述源极/漏极区之间的沟道区域上的区域的区域中; 以及形成在捕获膜上的栅电极。通过使用有机材料的低压CVD形成含有碳的氮化硅膜，以覆盖位于相邻栅电极之间的栅电极和捕获膜的一部分。

10. 发明授权

US07476943B2 Semiconductor device having diffusion layers as bit lines and method for manufacturing the same 失效
标题翻译：具有作为位线的扩散层的半导体器件及其制造方法
公开(公告)号：US07476943B2
公开(公告)日：2009-01-13
申请号：US11405451
申请日：2006-04-18
申请人： Nobuyoshi Takahashi , Fumihiko Noro , Kenji Sato
发明人： Nobuyoshi Takahashi , Fumihiko Noro , Kenji Sato
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L27/115
摘要： A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.
摘要翻译：半导体器件包括：半导体区域; 多个位线扩散层，其形成在所述半导体区域的上部，并且各自沿行方向延伸; 形成在位线扩散层上的多个位线绝缘膜; 形成在所述半导体区域上的各个相邻位线扩散层之间的多个栅极绝缘膜; 以及多个字线，各自在列方向上形成在半导体区域上，并且与字线绝缘膜和栅极绝缘膜交叉。存储单元形成在栅极绝缘膜和字线的交点处。包括与位线扩散层电连接的连接部分的多个连接扩散层形成在半导体区域的上部，并且连接部分的上表面的电平低于连接扩散部的上表面的高度半导体区域中的层。

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