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1. 发明申请

US20070082477A1 Integrated circuit fabricating techniques employing sacrificial liners 审中-公开
标题翻译：采用牺牲衬垫的集成电路制造技术
公开(公告)号：US20070082477A1
公开(公告)日：2007-04-12
申请号：US11245712
申请日：2005-10-06
申请人： Mehul Naik , Srinivas Gandikota , Girish Dixit , Dennis Yost
发明人： Mehul Naik , Srinivas Gandikota , Girish Dixit , Dennis Yost
IPC分类号： H01L21/4763 , H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/76808 , H01L21/76877
摘要： The present invention provides techniques for fabricating integrated circuit structures in semiconductor wafer fabrication. A via hole is prepared in a dielectric stack having a bottom via etch stop layer. The via hole is not extended through the via etch stop layer at this stage of the process. The via hole is partly filled with a sacrificial via fill such that a recess without sacrificial via fill is formed in the top portion of the via hole. A substantially conformal sacrificial layer is deposited on the top surface of the dielectric stack and in the recess. Then, a photoresist layer is deposited on the sacrificial fill. A trench etch mask overlaying the via hole, is developed in the photoresist layer. This mask is etched through the sacrificial layer that is formed on the top surface of the dielectric stack as well as through the sacrificial fill and sacrificial layer that is present in the via hole. Additionally, the mask is employed for etching a trench partly through the dielectric layer thereby forming a trench and an underlying via hole. The via hole is then extended through the via etch stop layer. Subsequently, the photoresist layer and the sacrificial layer are removed from the top surface of the dielectric stack resulting in a trench and underlying via hole that is suitable for fabricating a dual damascene structure. Alternatively, a recess can be formed by depositing a substantially conformal sacrificial layer on the top surface of the dielectric stack and in the via hole to form a lined via hole. The lined via hole is then partly filled with a sacrificial via fill such that a recess without sacrificial via fill is formed in the top portion of the lined via hole. Next, a photoresist layer is deposited in the recess and on the sacrificial liner that is deposited on the top surface of the dielectric stack.
摘要翻译：本发明提供了在半导体晶片制造中制造集成电路结构的技术。在具有底部通孔蚀刻停止层的电介质叠层中制备通孔。在该过程的这个阶段，通孔不延伸穿过通孔蚀刻停止层。通孔部分地填充有牺牲通孔填充物，使得在通孔的顶部部分中形成没有牺牲通孔填充物的凹部。基本上共形的牺牲层沉积在电介质叠层的顶表面和凹槽中。然后，在牺牲填充物上沉积光致抗蚀剂层。在光致抗蚀剂层中显影覆盖通孔的沟槽蚀刻掩模。该掩模通过形成在电介质堆叠的顶表面上的牺牲层以及穿过存在于通孔中的牺牲填充层和牺牲层进行蚀刻。此外，掩模用于部分地通过介电层蚀刻沟槽，从而形成沟槽和下面的通孔。然后通孔穿过通孔蚀刻停止层。随后，从电介质堆叠的顶表面去除光致抗蚀剂层和牺牲层，产生适于制造双镶嵌结构的沟槽和下面的通孔。或者，可以通过在电介质堆叠的顶表面上和通孔中沉积基本上共形的牺牲层来形成凹槽，以形成衬里的通孔。然后将衬里的通孔部分地填充有牺牲通孔填充物，使得在衬里通孔的顶部部分中形成没有牺牲通孔填充物的凹部。接下来，将光致抗蚀剂层沉积在沉积在电介质堆叠的顶表面上的凹部和牺牲衬垫上。

2. 发明授权

US06905622B2 Electroless deposition method 有权
公开(公告)号：US06905622B2
公开(公告)日：2005-06-14
申请号：US10117712
申请日：2002-04-03
申请人： Deenesh Padhi , Joseph Yahalom , Sivakami Ramanathan , Chris R. McGuirk , Srinivas Gandikota , Girish Dixit
发明人： Deenesh Padhi , Joseph Yahalom , Sivakami Ramanathan , Chris R. McGuirk , Srinivas Gandikota , Girish Dixit
IPC分类号： C23C18/16 , H01L21/02 , H01L21/285 , H01L21/288 , H01L21/306 , H01L21/321 , H01L21/768 , B44C1/22 , B05D3/04 , B05D3/10
CPC分类号： H01L21/02074 , C23C18/1694 , C23C18/1831 , C23C18/1834 , C23C18/1851 , C23C18/1879 , C23C18/1882 , C23C18/1893 , C23C18/31 , C23C18/34 , C23C18/36 , C23C18/50 , H01L21/02068 , H01L21/28518 , H01L21/288 , H01L21/76843 , H01L21/76849 , H01L21/76874 , H01L2221/1089
摘要： Methods and apparatus are provided for forming a metal or metal silicide layer by an electroless deposition technique. In one aspect, a method is provided for processing a substrate including depositing an initiation layer on a substrate surface, cleaning the substrate surface, and depositing a conductive material on the initiation layer by exposing the initiation layer to an electroless solution. The method may further comprise etching the substrate surface with an acidic solution and cleaning the substrate of the acidic solution prior to depositing the initiation layer. The initiation layer may be formed by exposing the substrate surface to a noble metal electroless solution or a borane-containing solution. The conductive material may be deposited with a borane-containing reducing agent. The conductive material may be used as a passivation layer, a barrier layer, a seed layer, or for use in forming a metal silicide layer.

3. 发明授权

US06899816B2 Electroless deposition method 有权
标题翻译：无电沉积法
公开(公告)号：US06899816B2
公开(公告)日：2005-05-31
申请号：US10117711
申请日：2002-04-03
申请人： Deenesh Padhi , Joseph Yahalom , Sivakami Ramanathan , Chris R. McGuirk , Srinivas Gandikota , Girish Dixit
发明人： Deenesh Padhi , Joseph Yahalom , Sivakami Ramanathan , Chris R. McGuirk , Srinivas Gandikota , Girish Dixit
IPC分类号： C23C18/18 , H01L21/285 , H01L21/288 , H01L21/336 , H01L21/768 , B44C1/22 , B05D3/04 , B05D3/10
CPC分类号： H01L21/76843 , C23C18/1651 , C23C18/1893 , H01L21/28518 , H01L21/288 , H01L21/76849 , H01L21/76874 , H01L29/665 , H01L2221/1089
摘要： Methods and apparatus are provided for forming a metal or metal silicide layer by an electroless deposition technique. In one aspect, a method is provided for processing a substrate including depositing an initiation layer on a substrate surface, cleaning the substrate surface, and depositing a conductive material on the initiation layer by exposing the initiation layer to an electroless solution. The method may further comprise etching the substrate surface with an acidic solution and cleaning the substrate of the acidic solution prior to depositing the initiation layer. The initiation layer may be formed by exposing the substrate surface to a noble metal electroless solution or a borane-containing solution. The conductive material may be deposited with a borane-containing reducing agent. The conductive material may be used as a passivation layer, a barrier layer, a seed layer, or for use in forming a metal silicide layer.
摘要翻译：提供了通过无电沉积技术形成金属或金属硅化物层的方法和装置。在一个方面，提供了一种用于处理衬底的方法，包括在衬底表面上沉积起始层，清洁衬底表面，以及通过将引发层暴露于无电镀溶液而在引发层上沉积导电材料。该方法可以进一步包括用酸性溶液蚀刻衬底表面并在沉积起始层之前清洁酸性溶液的衬底。起始层可以通过将基材表面暴露于贵金属化学电解溶液或含硼烷溶液来形成。导电材料可以用含硼烷的还原剂沉积。导电材料可以用作钝化层，阻挡层，种子层，或用于形成金属硅化物层。

4. 发明授权

US06797620B2 Method and apparatus for improved electroplating fill of an aperture 失效
标题翻译：用于改善孔的电镀填充物的方法和装置
公开(公告)号：US06797620B2
公开(公告)日：2004-09-28
申请号：US10124095
申请日：2002-04-16
申请人： John S. Lewis , Srinivas Gandikota , Sivakami Ramanathan , Girish Dixit , Robin Cheung , Fusen Chen
发明人： John S. Lewis , Srinivas Gandikota , Sivakami Ramanathan , Girish Dixit , Robin Cheung , Fusen Chen
IPC分类号： H01L2144
CPC分类号： H01L21/2855 , H01L21/76879
摘要： A method and apparatus is provided for filling apertures formed in a substrate surface by depositing materials that selectively inhibit or limit the formation or growth of subsequent layers used to fill an aperture. In one aspect, a method is provided for processing a substrate including providing a substrate having a field and apertures formed therein, wherein the apertures each have a bottom and sidewalls, depositing a seed layer on the bottom and sidewalls of the apertures, depositing a growth-inhibiting layer on at least one of the field of the substrate or an upper portion of the sidewalls of the apertures, and depositing a conductive layer on the growth-inhibiting layer and the seed layer. Deposition of the growth-inhibiting layer improves fill of the aperture from the bottom of the aperture up to the field of the substrate.
摘要翻译：提供了一种方法和装置，用于通过沉积选择性地抑制或限制用于填充孔的后续层的形成或生长的材料来填充形成在衬底表面中的孔。在一个方面，提供了一种用于处理衬底的方法，包括提供具有形成在其中的场和孔的衬底，其中每个孔具有底部和侧壁，在孔的底部和侧壁上沉积种子层，沉积生长在衬底的场中的至少一个或孔的侧壁的上部中的至少一个上的抑制层，并且在生长抑制层和种子层上沉积导电层。生长抑制层的沉积改善了孔的填充，从孔的底部到基底的场。

5. 发明申请

US20050136185A1 Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application 审中-公开
标题翻译：后冲洗以改善无电钴在铜上的选择性沉积，用于ULSI应用
公开(公告)号：US20050136185A1
公开(公告)日：2005-06-23
申请号：US10979078
申请日：2004-10-29
申请人： Sivakami Ramanathan , Deenesh Padhi , Srinivas Gandikota , Girish Dixit
发明人： Sivakami Ramanathan , Deenesh Padhi , Srinivas Gandikota , Girish Dixit
IPC分类号： B05D1/40 , B05D3/00 , C23C18/16 , C23C18/31 , C23C18/44 , C23C18/50 , C23G1/10 , H01L21/288 , H01L21/302 , H01L21/31 , H01L21/44 , H01L21/461 , H01L21/768
CPC分类号： H01L21/76877 , C23C18/166 , C23C18/1831 , C23C18/1834 , C23C18/1879 , C23C18/1882 , C23C18/34 , C23C18/36 , C23C18/44 , C23C18/50 , C23G1/10 , H01L21/288 , H01L21/76814 , H01L21/76849 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L21/76883
摘要： A method for depositing a passivation layer on a substrate surface using one or more electroplating techniques is provided. Embodiments of the method include selectively depositing an initiation layer on a conductive material by exposing the substrate surface to a first electroless solution, depositing a passivating material on the initiation layer by exposing the initiation layer to a second electroless solution, and cleaning the substrate surface with an acidic solution. In another aspect, the method includes applying ultrasonic or megasonic energy to the substrate surface during the application of the acidic solution. In still another aspect, the method includes using the acidic solution to remove between about 100 Å and about 200 Å of the passivating material. In yet another aspect, the method includes cleaning the substrate surface with a first acidic solution prior to the deposition of the initiation layer.
摘要翻译：提供了使用一种或多种电镀技术在衬底表面上沉积钝化层的方法。该方法的实施例包括通过将衬底表面暴露于第一无电解溶液来选择性地沉积引发层，通过将引发层暴露于第二无电解溶液来沉积起始层上的钝化材料，并用酸性溶液。在另一方面，该方法包括在施加酸性溶液期间将超声波或兆声波能量施加到基底表面。在另一方面，该方法包括使用酸性溶液去除大约至大约200埃的钝化材料。在另一方面，该方法包括在沉积起始层之前用第一酸性溶液清洗基底表面。

6. 发明授权

US07205228B2 Selective metal encapsulation schemes 失效
标题翻译：选择性金属封装方案
公开(公告)号：US07205228B2
公开(公告)日：2007-04-17
申请号：US10812480
申请日：2004-03-30
申请人： Deenesh Padhi , Srinivas Gandikota , Mehul Naik , Suketu A. Parikh , Girish A. Dixit
发明人： Deenesh Padhi , Srinivas Gandikota , Mehul Naik , Suketu A. Parikh , Girish A. Dixit
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/288 , H01L21/76829 , H01L21/7685 , H01L21/76885
摘要： A method and system of processing a semiconductor substrate includes, in one or more embodiments, depositing a protective layer on the substrate surface comprising a conductive element disposed in a dielectric material; processing the protective layer to expose the conductive element; electrolessly depositing a metallic passivating layer onto the conductive element; and removing at least a portion of the protective layer from the substrate after electroless deposition. In another aspect, a method and system of processing a semiconductor includes depositing a metallic passivating layer onto a substrate surface comprising a conductive element, masking the passivating layer to protect the underlying conductive element of the substrate surface, removing the unmasked passivating layer, and removing the mask from the passivating layer.
摘要翻译：在一个或多个实施例中，处理半导体衬底的方法和系统包括在衬底表面上沉积保护层，所述保护层包括布置在电介质材料中的导电元件; 处理所述保护层以暴露所述导电元件; 将金属钝化层无电沉积到导电元件上; 以及在无电沉积之后从衬底去除保护层的至少一部分。在另一方面，一种处理半导体的方法和系统包括在包括导电元件的衬底表面上沉积金属钝化层，掩蔽钝化层以保护衬底表面的下面的导电元件，去除未屏蔽的钝化层，以及去除掩模从钝化层。

7. 发明授权

US09330939B2 Method of enabling seamless cobalt gap-fill 有权
标题翻译：实现无缝钴填隙的方法
公开(公告)号：US09330939B2
公开(公告)日：2016-05-03
申请号：US13786644
申请日：2013-03-06
申请人： Bhushan N. Zope , Avgerinos V. Gelatos , Bo Zheng , Yu Lei , Xinyu Fu , Srinivas Gandikota , Sang-Ho Yu , Mathew Abraham
发明人： Bhushan N. Zope , Avgerinos V. Gelatos , Bo Zheng , Yu Lei , Xinyu Fu , Srinivas Gandikota , Sang-Ho Yu , Mathew Abraham
IPC分类号： H01L21/76 , H01L21/48 , H01L21/02 , H01L21/768 , H01L21/285
CPC分类号： H01L21/76879 , H01L21/02057 , H01L21/2855 , H01L21/28556 , H01L21/4846 , H01L21/76814 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76877 , H01L21/76883 , H01L23/53209 , H01L23/5329 , H01L29/66621
摘要： Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a contact metal layer on a substrate and annealing the contact metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the contact metal layer on the substrate, exposing the portion of the contact metal layer to a plasma treatment process, and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the contact metal layer to a plasma treatment process until a predetermined thickness of the contact metal layer is achieved.
摘要翻译：提供了在半导体器件的接触结构中沉积接触金属层的方法。在一个实施例中，提供了一种在半导体器件中沉积用于形成接触结构的接触金属层的方法。该方法包括进行循环金属沉积工艺，以将接触金属层沉积在衬底上并退火设置在衬底上的接触金属层。循环金属沉积工艺包括将衬底暴露于沉积前体气体混合物以将接触金属层的一部分沉积在衬底上，将接触金属层的该部分暴露于等离子体处理工艺，并重复将衬底暴露于沉积前体气体混合物，并将接触金属层的部分暴露于等离子体处理工艺，直到实现接触金属层的预定厚度。

8. 发明申请

US20140017408A1 Deposition Of N-Metal Films Comprising Aluminum Alloys 有权
标题翻译：包含铝合金的N-金属膜的沉积
公开(公告)号：US20140017408A1
公开(公告)日：2014-01-16
申请号：US13930194
申请日：2013-06-28
申请人： Srinivas Gandikota , Xinliang Lu , Shih Chung Chen , Wei Tang , Jing Zhou , Seshadri Ganguli , David Thompson , Jeffrey W. Anthis , Atif Noori , Faruk Gungor , Dien-Yeh Wu , Mei Chang , Xinyu Fu , Yu Lei
发明人： Srinivas Gandikota , Xinliang Lu , Shih Chung Chen , Wei Tang , Jing Zhou , Seshadri Ganguli , David Thompson , Jeffrey W. Anthis , Atif Noori , Faruk Gungor , Dien-Yeh Wu , Mei Chang , Xinyu Fu , Yu Lei
IPC分类号： C23C18/00
CPC分类号： C23C18/00 , C23C16/08 , C23C16/18 , C23C16/45527 , C23C16/45534 , C23C16/45553
摘要： Provided are methods of depositing films comprising alloys of aluminum, which may be suitable as N-metal films. Certain methods comprise exposing a substrate surface to a metal halide precursor comprising a metal halide selected from TiCl4, TaCl5 and HfCl4 to provide a metal halide at the substrate surface; purging metal halide; exposing the substrate surface to an alkyl aluminum precursor comprising one or more of dimethyaluminum hydride, diethylhydridoaluminum, methyldihydroaluminum, and an alkyl aluminum hydrides of the formula [(CxHy)3-aAlHa]n, wherein x has a value of 1 to 3, y has a value of 2x+2, a has a value of 1 to 2, and n has a value of 1 to 4; and exposing the substrate surface to an alane-containing precursor comprising one or more of dimethylethylamine alane, methylpyrrolidinealane, di(methylpyrolidine)alane, and trimethyl amine alane borane. Other methods comprise exposing a substrate surface to a metal precursor and trimethyl amine alane borane.
摘要翻译：提供了沉积包括铝合金的膜的方法，其可以适合作为N-金属膜。某些方法包括将衬底表面暴露于包含选自TiCl 4，TaCl 5和HfCl 4的金属卤化物的金属卤化物前体，以在衬底表面提供金属卤化物; 清洗金属卤化物; 将基材表面暴露于包含一种或多种二氢化铝氢化物，二乙基氢化铝，甲基二氢铝和式[（C x H y）3-a AlHa] n的烷基铝氢化物的烷基铝前体，其中x具有1至3的值，y 具有2x + 2的值，a具有1至2的值，并且n具有1至4的值; 并将基材表面暴露于含有二甲基乙基胺丙烷，甲基吡咯烷烃，二（甲基吡咯烷）甲烷和三甲基胺丙烷硼烷中的一种或多种的含Alane的前体。其他方法包括将基底表面暴露于金属前体和三甲基胺丙烷硼烷。

9. 发明授权

US08580094B2 Magnetron design for RF/DC physical vapor deposition 有权
标题翻译：用于RF / DC物理气相沉积的磁控管设计
公开(公告)号：US08580094B2
公开(公告)日：2013-11-12
申请号：US13163817
申请日：2011-06-20
申请人： Rongjun Wang , Sally Lou , Muhammad Rasheed , Jianxin Lei , Xianmin Tang , Srinivas Gandikota , Ryan Hanson , Tza-Jing Gung , Keith A. Miller , Thanh X. Nguyen
发明人： Rongjun Wang , Sally Lou , Muhammad Rasheed , Jianxin Lei , Xianmin Tang , Srinivas Gandikota , Ryan Hanson , Tza-Jing Gung , Keith A. Miller , Thanh X. Nguyen
IPC分类号： C23C14/35
CPC分类号： C23C14/35 , H01J37/3408 , H01J37/345 , H01J37/3461
摘要： Methods and apparatus to improve target life and deposition uniformity in PVD chambers are provided herein. In some embodiments, a magnetron assembly includes a shunt plate having a central axis, the shunt plate rotatable about the central axis, a first open loop magnetic pole arc coupled to the shunt plate at a first radius from the central axis, and a second open loop magnetic pole arc coupled the shunt plate at a first distance from the first open loop magnetic pole arc, wherein at least one of the first radius varies along the first open loop magnetic pole arc or the first distance varies along the second open loop magnetic pole arc. In some embodiments, a first polarity of the first open loop magnetic pole arc opposes a second polarity of the second open loop magnetic pole arc.
摘要翻译：本文提供了改善PVD室中的目标寿命和沉积均匀性的方法和装置。在一些实施例中，磁控管组件包括具有中心轴线的分流板，分流板可围绕中心轴线旋转，第一开环磁极电弧在与中心轴线成第一半径处耦合到分流板，第二开路环形磁极以与第一开环磁极弧成第一距离的方式将分流板电弧耦合，其中第一半径中的至少一个沿第一开环磁极弧变化，或者第一距离沿第二开环磁极变化弧。在一些实施例中，第一开环磁极的第一极性与第二开环磁极的第二极性相反。

10. 发明申请

US20130157460A1 METHODS FOR ANNEALING A METAL CONTACT LAYER TO FORM A METAL SILICIDATION LAYER 有权
标题翻译：用于退火金属接触层以形成金属硅酸盐层的方法
公开(公告)号：US20130157460A1
公开(公告)日：2013-06-20
申请号：US13714588
申请日：2012-12-14
申请人： Xinyu Fu , Wei Tang , Kavita Shah , Srinivas Gandikota , San H. Yu , Avgerinos Gelatos
发明人： Xinyu Fu , Wei Tang , Kavita Shah , Srinivas Gandikota , San H. Yu , Avgerinos Gelatos
IPC分类号： H01L29/40
CPC分类号： H01L29/401 , H01L21/28052
摘要： Methods for annealing a contact metal layer for a metal silicidation process are provided in the present invention. In one embodiment, a method for annealing a contact metal layer for a silicidation process in a semiconductor device includes providing a substrate having a contact metal layer disposed thereon in a thermal annealing processing chamber, providing a heat energy to the contact metal layer in the thermal processing chamber, supplying a gas mixture including a nitrogen gas and a hydrogen gas while providing the heat energy to the contact layer in the thermal processing chamber, wherein the nitrogen gas and the hydrogen gas is supplied at a ratio between about 1:10 and about 1:1, and forming a metal silicide layer on the substrate.
摘要翻译：在本发明中提供了用于退火金属硅化工艺的接触金属层的方法。在一个实施例中，一种用于对半导体器件中的硅化工艺的接触金属层进行退火的方法包括：在热退火处理室中提供其上设置有接触金属层的基板，在该热退火处理室中向该接触金属层提供热能处理室，供给包括氮气和氢气的气体混合物，同时向热处理室中的接触层提供热能，其中氮气和氢气以约1:10和约 1：1，并在衬底上形成金属硅化物层。

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