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    • 2. 发明授权
    • Method for manufacturing semiconductor device
    • 制造半导体器件的方法
    • US06887767B2
    • 2005-05-03
    • US10392878
    • 2003-03-21
    • Mayumi NakasatoKazuhiro SasadaMasahiro Oda
    • Mayumi NakasatoKazuhiro SasadaMasahiro Oda
    • H01L21/76H01L21/762
    • H01L21/76235
    • A method for manufacturing a semiconductor device including forming a buffer film on a semiconductor substrate, forming a element partitioning trench, forming a oxidized film on the surface of the element partitioning trench, and washing the semiconductor substrate with hydrofluoric acid. The washing removes part of the buffer film, and the end of the buffer film is inwardly removed from the top edge of the element partitioning trench by a predetermined distance. The distance and the thickness of the oxidized film are represented by the expression 0≦x≦(d/2 sin θ), where x represents the distance, and θ represents the angle between a plane parallel to the semiconductor substrate and a side surface of the element partitioning trench.
    • 一种制造半导体器件的方法,包括在半导体衬底上形成缓冲膜,形成元件分隔沟槽,在元件分隔沟槽的表面上形成氧化膜,并用氢氟酸洗涤半导体衬底。 洗涤物去除部分缓冲膜,缓冲膜的端部从元件分隔槽的顶部边缘向内移除预定距离。 氧化膜的距离和厚度由表达式0 <= x <=(d /2sinθ)表示,其中x表示距离,θ表示平行于半导体衬底的平面与侧面之间的角度 元件分隔沟的表面。
    • 3. 发明授权
    • Method of fabricating semiconductor device having element isolation trench
    • 制造具有元件隔离沟槽的半导体器件的方法
    • US06613635B2
    • 2003-09-02
    • US10015756
    • 2001-12-17
    • Masahiro OdaKazuhiro Sasada
    • Masahiro OdaKazuhiro Sasada
    • H01L21336
    • H01L21/823878H01L21/76237H01L21/823807
    • Threshold voltage fluctuation in upper corner portions of a trench isolation is inhibited by rounding upper corner portions of the trench by thermal oxidation, introducing a first impurity into both upper corner portions of the trench and heat-treating the semiconductor substrate. Embodiments include increasing the threshold voltage in the upper corner portion of the trench in an n-channel transistor, previously increased by rounding oxidation, and introducing a p-type impurity, thereby canceling the threshold voltage reduction resulting from diffusion of the impurity during heat-treating the semiconductor substrate. In a p-channel transistor, the threshold voltage in the upper corner portion of the trench is increased by rounding oxidation thereby canceling the threshold voltage reduction resulting from introduction of the p-type first impurity into both upper corner portions of the trench.
    • 沟槽隔离的上角部的阈值电压波动通过热氧化对沟槽的上角部进行四舍五入,将第一杂质引入槽的两个上角部并对半导体衬底进行热处理来抑制。 实施例包括增加先前通过四舍五入氧化增加的n沟道晶体管中的沟槽的上角部分中的阈值电压,以及引入p型杂质,从而消除由于杂质在热处理期间的扩散而引起的阈值电压降低, 处理半导体衬底。 在p沟道晶体管中,通过舍入氧化来增加沟槽上角部分中的阈值电压,从而抵消由于将p型第一杂质引入沟槽的两个上角部而导致的阈值电压降低。
    • 6. 发明授权
    • Method for forming low-leakage impurity regions by sequence of high-and low-temperature treatments
    • 通过高温和低温处理顺序形成低泄漏杂质区的方法
    • US06342440B1
    • 2002-01-29
    • US09518246
    • 2000-03-03
    • Kazuhiro SasadaYasunori InoueShinichi TanimotoAtsuhiro NishidaYoshikazu Ibara
    • Kazuhiro SasadaYasunori InoueShinichi TanimotoAtsuhiro NishidaYoshikazu Ibara
    • H01L21425
    • H01L29/6659H01L21/26513H01L21/324H01L21/8234H01L29/665
    • A method of manufacturing a semiconductor device capable of suppressing increase of a leakage current resulting from a high-temperature heat treatment is obtained. In this manufacturing method, an impurity region is formed by selectively ion-implanting an impurity into the main surface of a semiconductor substrate. The impurity region is activated by performing a high-temperature heat treatment. The semiconductor device is recovered from crystal defects resulting from the high-temperature heat treatment by performing a low-temperature heat treatment after performing the high-temperature heat treatment. According to this manufacturing method, the semiconductor device is recovered from the crystal defects resulting from the ion implantation by the high-temperature heat treatment, and recovered from the crystal defects resulting from the high-temperature heat treatment by the low-temperature heat treatment. Thus, increase of a leakage current caused by the crystal defects resulting from the high-temperature heat treatment can be effectively prevented.
    • 获得能够抑制由高温热处理引起的漏电流增加的半导体装置的制造方法。 在该制造方法中,通过选择性地将杂质离子注入到半导体衬底的主表面中来形成杂质区。 通过进行高温热处理来激活杂质区域。 通过在进行高温热处理后进行低温热处理,从高温热处理得到的晶体缺陷中回收半导体装置。 根据该制造方法,通过高温热处理从离子注入产生的晶体缺陷中回收半导体器件,并且通过低温热处理从高温热处理引起的晶体缺陷中回收。 因此,可以有效地防止由高温热处理引起的晶体缺陷引起的漏电流的增加。
    • 7. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07968941B2
    • 2011-06-28
    • US12412659
    • 2009-03-27
    • Kazunori FujitaTomio YamashitaHaruki YonedaKazuhiro Sasada
    • Kazunori FujitaTomio YamashitaHaruki YonedaKazuhiro Sasada
    • H01L29/76
    • H01L29/7816H01L29/0696H01L29/0878H01L29/1095H01L29/42368H01L29/4238H01L29/66681
    • A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.
    • 半导体器件包括:外延层; 形成在外延层中的体层,其包括沟道区; 源层,叠加在体层上; 形成在外延层上的栅极绝缘体,其围绕源极层呈环形; 通过栅极绝缘体形成的栅电极; 在外延层中形成的漂移层,该外延层围绕主体层呈环状; 以及形成在所述外延层的表面中并且与所述源极层相对设置的漏极层。 主体层被布置成使得栅极宽度方向上的端部处的边界表面与栅极绝缘体的下表面接触。 栅极绝缘体至少在栅极绝缘体与栅极宽度端部处的主体层的边界面接触的部分中具有比栅极长度方向上的沟道区域上方的部分更厚的厚膜部分 方向。
    • 8. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20090242981A1
    • 2009-10-01
    • US12412659
    • 2009-03-27
    • Kazunori FujitaTomio YamashitaHaruki YonedaKazuhiro Sasada
    • Kazunori FujitaTomio YamashitaHaruki YonedaKazuhiro Sasada
    • H01L29/78
    • H01L29/7816H01L29/0696H01L29/0878H01L29/1095H01L29/42368H01L29/4238H01L29/66681
    • A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.
    • 半导体器件包括:外延层; 形成在外延层中的体层,其包括沟道区; 源层,叠加在体层上; 形成在外延层上的栅极绝缘体,其围绕源极层呈环形; 通过栅极绝缘体形成的栅电极; 在外延层中形成的漂移层,该外延层围绕主体层呈环状; 以及形成在所述外延层的表面中并且与所述源极层相对设置的漏极层。 主体层被布置成使得栅极宽度方向上的端部处的边界表面与栅极绝缘体的下表面接触。 栅极绝缘体至少在栅极绝缘体与栅极宽度端部处的主体层的边界面接触的部分中具有比栅极长度方向上的沟道区域上方的部分更厚的厚膜部分 方向。