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1. 发明授权

US07968941B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07968941B2
公开(公告)日：2011-06-28
申请号：US12412659
申请日：2009-03-27
申请人： Kazunori Fujita , Tomio Yamashita , Haruki Yoneda , Kazuhiro Sasada
发明人： Kazunori Fujita , Tomio Yamashita , Haruki Yoneda , Kazuhiro Sasada
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66681
摘要： A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.
摘要翻译：半导体器件包括：外延层; 形成在外延层中的体层，其包括沟道区; 源层，叠加在体层上; 形成在外延层上的栅极绝缘体，其围绕源极层呈环形; 通过栅极绝缘体形成的栅电极; 在外延层中形成的漂移层，该外延层围绕主体层呈环状; 以及形成在所述外延层的表面中并且与所述源极层相对设置的漏极层。主体层被布置成使得栅极宽度方向上的端部处的边界表面与栅极绝缘体的下表面接触。栅极绝缘体至少在栅极绝缘体与栅极宽度端部处的主体层的边界面接触的部分中具有比栅极长度方向上的沟道区域上方的部分更厚的厚膜部分方向。

2. 发明申请

US20090242981A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090242981A1
公开(公告)日：2009-10-01
申请号：US12412659
申请日：2009-03-27
申请人： Kazunori Fujita , Tomio Yamashita , Haruki Yoneda , Kazuhiro Sasada
发明人： Kazunori Fujita , Tomio Yamashita , Haruki Yoneda , Kazuhiro Sasada
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66681
摘要： A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.
摘要翻译：半导体器件包括：外延层; 形成在外延层中的体层，其包括沟道区; 源层，叠加在体层上; 形成在外延层上的栅极绝缘体，其围绕源极层呈环形; 通过栅极绝缘体形成的栅电极; 在外延层中形成的漂移层，该外延层围绕主体层呈环状; 以及形成在所述外延层的表面中并且与所述源极层相对设置的漏极层。主体层被布置成使得栅极宽度方向上的端部处的边界表面与栅极绝缘体的下表面接触。栅极绝缘体至少在栅极绝缘体与栅极宽度端部处的主体层的边界面接触的部分中具有比栅极长度方向上的沟道区域上方的部分更厚的厚膜部分方向。

3. 发明授权

US08525259B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08525259B2
公开(公告)日：2013-09-03
申请号：US12787052
申请日：2010-05-25
申请人： Yasuhiro Takeda , Kazunori Fujita , Haruki Yoneda
发明人： Yasuhiro Takeda , Kazunori Fujita , Haruki Yoneda
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7823
摘要： The invention prevents a source-drain breakdown voltage of a DMOS transistor from decreasing due to dielectric breakdown in a portion of a N type drift layer having high concentration formed in an active region near field oxide film corner portions surrounding an gate width end portion. The field oxide film corner portions are disposed on the outside of the gate width end portion so as to be further away from a P type body layer formed in the gate width end portion by forming the active region wider on the outside of the gate width end portion than in a gate width center portion. By this, the N type drift layer having high concentration near the field oxide film corner portions are disposed further away from the P type body layer without increasing the device area.
摘要翻译：本发明防止DMOS晶体管的源极 - 漏极击穿电压由于在围绕栅极宽度端部的场氧化物膜角部附近的有源区域中形成的具有高浓度的N型漂移层的部分中的电介质击穿而减小。通过在栅极宽度端部的外侧形成更宽的有源区域，将场氧化膜角部设置在栅极宽度端部的外侧，以便进一步远离形成在栅极宽度端部的P型主体层部分比在门宽中心部分。由此，在场氧化膜角部附近具有高浓度的N型漂移层配置为远离P型体层而不增加器件面积。

4. 发明申请

US20100301411A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100301411A1
公开(公告)日：2010-12-02
申请号：US12787052
申请日：2010-05-25
申请人： Yasuhiro TAKEDA , Kazunori Fujita , Haruki Yoneda
发明人： Yasuhiro TAKEDA , Kazunori Fujita , Haruki Yoneda
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7823
摘要： The invention prevents a source-drain breakdown voltage of a DMOS transistor from decreasing due to dielectric breakdown in a portion of a N type drift layer having high concentration formed in an active region near field oxide film corner portions surrounding an gate width end portion. The field oxide film corner portions are disposed on the outside of the gate width end portion so as to be further away from a P type body layer formed in the gate width end portion by forming the active region wider on the outside of the gate width end portion than in a gate width center portion. By this, the N type drift layer having high concentration near the field oxide film corner portions are disposed further away from the P type body layer without increasing the device area.
摘要翻译：本发明防止DMOS晶体管的源极 - 漏极击穿电压由于在围绕栅极宽度端部的场氧化物膜角部附近的有源区域中形成的具有高浓度的N型漂移层的部分中的电介质击穿而减小。通过在栅极宽度端部的外侧形成更宽的有源区域，将场氧化膜角部设置在栅极宽度端部的外侧，以便进一步远离形成在栅极宽度端部的P型主体层部分比在门宽中心部分。由此，在场氧化膜角部附近具有高浓度的N型漂移层配置为远离P型体层而不增加器件面积。

5. 发明申请

US20080185638A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080185638A1
公开(公告)日：2008-08-07
申请号：US11965536
申请日：2007-12-27
申请人： Yoshikazu YAMAOKA , Satoru Shimada , Kazunori Fujita , Kazuhiro Sasada
发明人： Yoshikazu YAMAOKA , Satoru Shimada , Kazunori Fujita , Kazuhiro Sasada
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4236 , H01L21/2815 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7809 , H01L29/7813
摘要： A semiconductor device capable of inhibiting a fabricating process from complication while inhibiting the dielectric strength voltage of a insulating film from reduction is obtained. This semiconductor device includes a groove portion, an insulating film formed on a surface of the groove portion, a gate electrode and a source impurity region, wherein upper ends of the gate electrode, which are portions in contact with the insulating film, are each located at a position identical with or deeper than the range of an impurity introduced from a surface of a semiconductor substrate with respect to the insulating film in order to form the source impurity region and above a lower surface of the source impurity region.
摘要翻译：可以获得能够在抑制绝缘膜的介电强度电压降低的同时抑制制造工艺的复杂化的半导体器件。该半导体器件包括沟槽部分，形成在沟槽部分的表面上的绝缘膜，栅极电极和源极杂质区域，其中栅电极的与绝缘膜接触的部分的上端分别位于在与半导体衬底的表面相对于绝缘膜引入的杂质的范围相同或更深的位置处，以形成源极杂质区域和源极杂质区域的下表面之上。

6. 发明授权

US08319281B2 Semiconductor device with insulated gate formed within grooved portion formed therein 有权
标题翻译：具有绝缘栅的半导体器件形成在其中形成的沟槽部分内
公开(公告)号：US08319281B2
公开(公告)日：2012-11-27
申请号：US11965536
申请日：2007-12-27
申请人： Yoshikazu Yamaoka , Satoru Shimada , Kazunori Fujita , Kazuhiro Sasada
发明人： Yoshikazu Yamaoka , Satoru Shimada , Kazunori Fujita , Kazuhiro Sasada
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4236 , H01L21/2815 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7809 , H01L29/7813
摘要： A semiconductor device capable of inhibiting a fabricating process from complication while inhibiting the dielectric strength voltage of a insulating film from reduction is obtained. This semiconductor device includes a groove portion, an insulating film formed on a surface of the groove portion, a gate electrode and a source impurity region, wherein upper ends of the gate electrode, which are portions in contact with the insulating film, are each located at a position identical with or deeper than the range of an impurity introduced from a surface of a semiconductor substrate with respect to the insulating film in order to form the source impurity region and above a lower surface of the source impurity region.
摘要翻译：可以获得能够在抑制绝缘膜的介电强度电压降低的同时抑制制造工艺的复杂化的半导体器件。该半导体器件包括沟槽部分，形成在沟槽部分的表面上的绝缘膜，栅极电极和源极杂质区域，其中栅电极的与绝缘膜接触的部分的上端分别位于在与半导体衬底的表面相对于绝缘膜引入的杂质的范围相同或更深的位置处，以形成源极杂质区域和源极杂质区域的下表面之上。

7. 发明授权

US07655974B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07655974B2
公开(公告)日：2010-02-02
申请号：US11829310
申请日：2007-07-27
申请人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
发明人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
IPC分类号： H01L29/76
CPC分类号： H01L21/761 , H01L21/763 , H01L27/088 , H01L29/1087 , H01L29/41741 , H01L29/41766 , H01L29/66734 , H01L29/7809 , H01L29/7813
摘要： A semiconductor device that reduces the width of an isolation region between semiconductor elements. The semiconductor device includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a buried layer formed between the semiconductor substrate and the epitaxial layer, a first trench formed in the epitaxial layer so as to surround the buried layer, and an insulation film formed in the first trench.
摘要翻译：一种半导体器件，其减小半导体元件之间的隔离区域的宽度。半导体器件包括半导体衬底，形成在半导体衬底上的外延层，形成在半导体衬底和外延层之间的掩埋层，形成在外延层中以围绕掩埋层的第一沟槽，以及绝缘膜形成在第一个沟槽。

8. 发明授权

US07361992B2 Semiconductor device including interconnects formed by damascene process and manufacturing method thereof 有权
标题翻译：包括通过镶嵌工艺形成的互连的半导体器件及其制造方法
公开(公告)号：US07361992B2
公开(公告)日：2008-04-22
申请号：US10664875
申请日：2003-09-22
申请人： Naoteru Matsubara , Kazunori Fujita
发明人： Naoteru Matsubara , Kazunori Fujita
IPC分类号： H01L29/40
CPC分类号： H01L21/76807 , H01L21/76825 , H01L21/76826 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： After etching the interlayer dielectric film 4 formed on the lower layer interconnect line 1 into a shape with holes, the upper layer dielectric film 6 is etched into a shape with trenches utilizing the etching stopper 5. The etching stopper 5 which is exposed at the bottom of the trench is removed by additional etching, and then, the interlayer dielectric film 4 which is exposed at the bottom of the trench is etched back to a predetermined thickness. Subsequently, the hole and the trench are filled with an interconnect metal 10.
摘要翻译：在将下层布线1上形成的层间绝缘膜4蚀刻成具有孔的形状之后，将上层电介质膜6用蚀刻阻挡层5蚀刻成具有沟槽的形状。通过附加蚀刻去除在沟槽底部暴露的蚀刻阻挡层5，然后将在沟槽底部暴露的层间绝缘膜4回蚀刻到预定厚度。随后，孔和沟槽填充互连金属10。

9. 发明授权

US06559031B2 Method of fabricating semiconductor device having element isolation trench 有权
公开(公告)号：US06559031B2
公开(公告)日：2003-05-06
申请号：US09960494
申请日：2001-09-24
申请人： Kazunori Fujita
发明人： Kazunori Fujita
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A method of fabricating a semiconductor device capable of sufficiently rounding an opening upper end of an element isolation trench is obtained. This method of fabricating a semiconductor device comprises steps of forming an element isolation trench on a semiconductor substrate, performing thermal oxidation on at least an opening upper end of the element isolation trench while increasing the atmosphere temperature of the semiconductor substrate beyond a prescribed temperature thereby forming a first oxide film and suppressing formation of the first oxide film on the opening upper end before the atmosphere temperature is increased beyond the prescribed temperature. Thus, the semiconductor substrate is prevented from oxidation under a low temperature, whereby oxidation is more thickly performed by thermal oxidation in a high-temperature region while relaxing stress applied to the semiconductor substrate. Therefore, oxidation is thickly performed in the high-temperature region not reducing the oxidizing velocity for a corner portion, whereby the opening upper end of the element isolation trench can be sufficiently rounded.

10. 发明授权

US4493878A Fuel element for liquid fuel cell and a liquid fuel cell 失效
标题翻译：用于液体燃料电池和液体燃料电池的燃料元件
公开(公告)号：US4493878A
公开(公告)日：1985-01-15
申请号：US482723
申请日：1983-04-07
申请人： Tatsuo Horiba , Kazuo Iwamoto , Hidejiro Kawana , Kazunori Fujita , Kohki Tamura
发明人： Tatsuo Horiba , Kazuo Iwamoto , Hidejiro Kawana , Kazunori Fujita , Kohki Tamura
IPC分类号： H01M8/06 , H01M8/00 , H01M8/04 , H01M8/08 , H01M6/36
CPC分类号： H01M8/08 , H01M8/00 , H01M8/04186
摘要： This invention is a fuel element for liquid fuel cell characterized in that a liquid fuel is rendered to assume a non-fluidized state by either physical means or chemical means, and is returned back to the initial liquid fuel at any time by physical means or chemical means.
摘要翻译：本发明是一种用于液体燃料电池的燃料元件，其特征在于液体燃料通过物理手段或化学方式使其处于非流化状态，并随时通过物理手段或化学物质返回到初始液体燃料手段。

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