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1. 发明申请

US20090001590A1 WIRING STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：接线结构及其制造方法
公开(公告)号：US20090001590A1
公开(公告)日：2009-01-01
申请号：US12147122
申请日：2008-06-26
申请人： Tomio Yamashita , Mitsuaki Morigami
发明人： Tomio Yamashita , Mitsuaki Morigami
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76877 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A wiring structure includes a first wiring, a first interlayer dielectric film having a first opening, a second wiring formed with a first recess portion on a region corresponding to the first opening, a second interlayer dielectric film having a second opening and a third wiring so formed as to cover the second interlayer dielectric film, wherein an inner side surface of the second opening is arranged on a region corresponding to the first recess portion and formed such that an opening width of a portion in the vicinity of an upper end increases from a lower portion toward an upper portion.
摘要翻译：布线结构包括第一布线，具有第一开口的第一层间电介质膜，在与第一开口对应的区域上形成有第一凹部的第二布线，具有第二开口的第二层间绝缘膜和第三布线形成为覆盖第二层间电介质膜，其中第二开口的内侧表面布置在与第一凹部对应的区域上，并且形成为使得上端附近的部分的开口宽度从下部朝向上部。

2. 发明授权

US06921976B2 Semiconductor device including an island-like dielectric member embedded in a conductive pattern 有权
标题翻译：半导体器件包括嵌入导电图案中的岛状电介质部件
公开(公告)号：US06921976B2
公开(公告)日：2005-07-26
申请号：US10076355
申请日：2002-02-19
申请人： Tomio Yamashita
发明人： Tomio Yamashita
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L23/485 , H01L23/48
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05647 , H01L2224/13099 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48747 , H01L2224/48847 , H01L2224/85447 , H01L2924/00011 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/00 , H01L2924/00015
摘要： A method for manufacturing a semiconductor device having flat pads. An opening and island-like dielectric films are first formed in a dielectric film. The opening is then filled with metal, and a metal layer is formed on the dielectric film. The upper surface of the metal layer is flattened using the CMP technique with the upper surface of the dielectric film functioning as a stopper. The island-like dielectric films prevent the occurrence of dishing in a conductive portion.
摘要翻译：一种制造具有平垫的半导体器件的方法。首先在电介质膜中形成开口和岛状电介质膜。然后用金属填充开口，并且在电介质膜上形成金属层。使用CMP技术使金属层的上表面变平，电介质膜的上表面用作止动件。岛状电介质膜防止导电部分发生凹陷。

3. 发明授权

US06916743B2 Semiconductor device and method for manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06916743B2
公开(公告)日：2005-07-12
申请号：US10197575
申请日：2002-07-18
申请人： Tomio Yamashita , Yoshio Okayama
发明人： Tomio Yamashita , Yoshio Okayama
IPC分类号： H01L21/768 , H01L21/027 , H01L23/544 , H01L21/302
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing method that enables accurate recognition of an alignment mark and optimal formation of a buried wiring. The method includes depositing an insulation film above a semiconductor device, and then etching the insulation film to form a buried wiring hole and an alignment mark pit in the insulation film. Subsequently, a conductive film is deposited on the surface of the insulation film that includes the buried wiring hole and the alignment mark pit. The conductive film is deposited so that it is less than the depth of the alignment mark pit and less than half of a minimum opening width of the alignment mark pit.
摘要翻译：一种半导体器件制造方法，其能够精确地识别对准标记并最佳地形成埋入布线。该方法包括在半导体器件上沉积绝缘膜，然后蚀刻绝缘膜以在绝缘膜中形成掩埋布线孔和对准标记凹坑。随后，在包括掩埋布线孔和对准标记凹坑的绝缘膜的表面上沉积导电膜。导电膜被沉积成小于对准标记凹坑的深度并且小于对准标记凹坑的最小开口宽度的一半。

4. 发明授权

US07968941B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07968941B2
公开(公告)日：2011-06-28
申请号：US12412659
申请日：2009-03-27
申请人： Kazunori Fujita , Tomio Yamashita , Haruki Yoneda , Kazuhiro Sasada
发明人： Kazunori Fujita , Tomio Yamashita , Haruki Yoneda , Kazuhiro Sasada
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66681
摘要： A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.
摘要翻译：半导体器件包括：外延层; 形成在外延层中的体层，其包括沟道区; 源层，叠加在体层上; 形成在外延层上的栅极绝缘体，其围绕源极层呈环形; 通过栅极绝缘体形成的栅电极; 在外延层中形成的漂移层，该外延层围绕主体层呈环状; 以及形成在所述外延层的表面中并且与所述源极层相对设置的漏极层。主体层被布置成使得栅极宽度方向上的端部处的边界表面与栅极绝缘体的下表面接触。栅极绝缘体至少在栅极绝缘体与栅极宽度端部处的主体层的边界面接触的部分中具有比栅极长度方向上的沟道区域上方的部分更厚的厚膜部分方向。

5. 发明授权

US07851917B2 Wiring structure and method of manufacturing the same 有权
标题翻译：接线结构及其制造方法
公开(公告)号：US07851917B2
公开(公告)日：2010-12-14
申请号：US12147122
申请日：2008-06-26
申请人： Tomio Yamashita , Mitsuaki Morigami
发明人： Tomio Yamashita , Mitsuaki Morigami
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76877 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A wiring structure includes a first wiring, a first interlayer dielectric film having a first opening, a second wiring formed with a first recess portion on a region corresponding to the first opening, a second interlayer dielectric film having a second opening and a third wiring so formed as to cover the second interlayer dielectric film, wherein an inner side surface of the second opening is arranged on a region corresponding to the first recess portion and formed such that an opening width of a portion in the vicinity of an upper end increases from a lower portion toward an upper portion.
摘要翻译：布线结构包括第一布线，具有第一开口的第一层间电介质膜，在与第一开口对应的区域上形成有第一凹部的第二布线，具有第二开口的第二层间绝缘膜和第三布线形成为覆盖第二层间电介质膜，其中第二开口的内侧表面布置在与第一凹部对应的区域上，并且形成为使得上端附近的部分的开口宽度从下部朝向上部。

6. 发明申请

US20090242981A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090242981A1
公开(公告)日：2009-10-01
申请号：US12412659
申请日：2009-03-27
申请人： Kazunori Fujita , Tomio Yamashita , Haruki Yoneda , Kazuhiro Sasada
发明人： Kazunori Fujita , Tomio Yamashita , Haruki Yoneda , Kazuhiro Sasada
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66681
摘要： A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.
摘要翻译：半导体器件包括：外延层; 形成在外延层中的体层，其包括沟道区; 源层，叠加在体层上; 形成在外延层上的栅极绝缘体，其围绕源极层呈环形; 通过栅极绝缘体形成的栅电极; 在外延层中形成的漂移层，该外延层围绕主体层呈环状; 以及形成在所述外延层的表面中并且与所述源极层相对设置的漏极层。主体层被布置成使得栅极宽度方向上的端部处的边界表面与栅极绝缘体的下表面接触。栅极绝缘体至少在栅极绝缘体与栅极宽度端部处的主体层的边界面接触的部分中具有比栅极长度方向上的沟道区域上方的部分更厚的厚膜部分方向。

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