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1. 发明授权

US08157978B2 Etching system and method for forming multiple porous semiconductor regions with different optical and structural properties on a single semiconductor wafer 有权
标题翻译：用于在单个半导体晶片上形成具有不同光学和结构特性的多个多孔半导体区域的蚀刻系统和方法
公开(公告)号：US08157978B2
公开(公告)日：2012-04-17
申请号：US12361736
申请日：2009-01-29
申请人： Matthew J. Sendelbach , Alok Vaid , Shahin Zangooie
发明人： Matthew J. Sendelbach , Alok Vaid , Shahin Zangooie
IPC分类号： C25D5/02 , C25D17/00
CPC分类号： C25F7/00 , C25F3/12 , C25F3/14 , H01L21/3063
摘要： Disclosed is an electrochemical etching system with localized etching capability. The system allows multiple different porous semiconductor regions to be formed on a single semiconductor wafer. Localized etching is achieved through the use of one or more stationary and/or movable computer-controlled inner containers operating within an outer container. The outer container holds the electrolyte solution and acts as an electrolyte supply source for the inner container(s). The inner container(s) limit the size of the etched region of the semiconductor wafer by confining the electric field. Additionally, the current amount passing through each inner container during the electrochemical etching process can be selectively adjusted to achieve a desired result within the etched region. Localized etching of sub-regions within each etched region can also be achieved through the use of different stationary and/or moveable electrode structures and shields within each inner container. Also disclosed are associated method embodiments.
摘要翻译：公开了具有局部蚀刻能力的电化学蚀刻系统。该系统允许在单个半导体晶片上形成多个不同的多孔半导体区域。通过使用在外部容器内操作的一个或多个固定和/或可移动计算机控制的内部容器来实现局部蚀刻。外部容器保持电解质溶液并用作内部容器的电解质供应源。内部容器通过限制电场来限制半导体晶片的蚀刻区域的尺寸。此外，可以选择性地调节在电化学蚀刻工艺期间通过每个内部容器的电流量，以在蚀刻区域内实现期望的结果。每个蚀刻区域内的子区域的局部蚀刻也可以通过在每个内部容器内使用不同的固定和/或可移动的电极结构和屏蔽来实现。还公开了相关联的方法实施例。

2. 发明申请

US20100187126A1 ETCHING SYSTEM AND METHOD FOR FORMING MULTIPLE POROUS SEMICONDUCTOR REGIONS WITH DIFFERENT OPTICAL AND STRUCTURAL PROPERTIES ON A SINGLE SEMICONDUCTOR WAFER 有权
标题翻译：用于在单个半导体波长上形成具有不同光学和结构特性的多个多孔半导体区域的蚀刻系统和方法
公开(公告)号：US20100187126A1
公开(公告)日：2010-07-29
申请号：US12361736
申请日：2009-01-29
申请人： Matthew J. Sendelbach , Alok Vaid , Shahin Zangooie
发明人： Matthew J. Sendelbach , Alok Vaid , Shahin Zangooie
IPC分类号： C25F3/12 , C25F7/00
CPC分类号： C25F7/00 , C25F3/12 , C25F3/14 , H01L21/3063
摘要： Disclosed is an electrochemical etching system with localized etching capability. The system allows multiple different porous semiconductor regions to be formed on a single semiconductor wafer. Localized etching is achieved through the use of one or more stationary and/or movable computer-controlled inner containers operating within an outer container. The outer container holds the electrolyte solution and acts as an electrolyte supply source for the inner container(s). The inner container(s) limit the size of the etched region of the semiconductor wafer by confining the electric field. Additionally, the current amount passing through each inner container during the electrochemical etching process can be selectively adjusted to achieve a desired result within the etched region. Localized etching of sub-regions within each etched region can also be achieved through the use of different stationary and/or moveable electrode structures and shields within each inner container. Also disclosed are associated method embodiments.
摘要翻译：公开了具有局部蚀刻能力的电化学蚀刻系统。该系统允许在单个半导体晶片上形成多个不同的多孔半导体区域。通过使用在外部容器内操作的一个或多个固定和/或可移动计算机控制的内部容器来实现局部蚀刻。外部容器保持电解质溶液并用作内部容器的电解质供应源。内部容器通过限制电场来限制半导体晶片的蚀刻区域的尺寸。此外，可以选择性地调节在电化学蚀刻工艺期间通过每个内部容器的电流量，以在蚀刻区域内实现期望的结果。每个蚀刻区域内的子区域的局部蚀刻也可以通过在每个内部容器内使用不同的固定和/或可移动的电极结构和屏蔽来实现。还公开了相关联的方法实施例。

3. 发明申请

US20130245806A1 AUTOMATED HYBRID METROLOGY FOR SEMICONDUCTOR DEVICE FABRICATION 有权
标题翻译：用于半导体器件制造的自动化混合规格
公开(公告)号：US20130245806A1
公开(公告)日：2013-09-19
申请号：US13419286
申请日：2012-03-13
申请人： Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender N. Rana
发明人： Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender N. Rana
IPC分类号： G06F19/00
CPC分类号： H01L22/12 , G03F7/70625 , H01L22/20
摘要： Methods and systems are provided for fabricating and measuring features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves fabricating a feature of the semiconductor device structure on a wafer of semiconductor material, determining a hybrid recipe for measuring the feature, configuring a plurality of metrology tools to implement the hybrid recipe; and obtaining a hybrid measurement of the feature in accordance with the hybrid recipe.
摘要翻译：提供了用于制造和测量半导体器件结构的特征的方法和系统。制造半导体器件结构的示例性方法包括在半导体材料的晶片上制造半导体器件结构的特征，确定用于测量特征的混合配方，配置多个计量工具以实现混合配方; 以及根据所述混合配方获得所述特征的混合测量。

4. 发明授权

US09330985B2 Automated hybrid metrology for semiconductor device fabrication 有权
标题翻译：用于半导体器件制造的自动混合测量
公开(公告)号：US09330985B2
公开(公告)日：2016-05-03
申请号：US13419286
申请日：2012-03-13
申请人： Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender N. Rana
发明人： Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender N. Rana
IPC分类号： G06F19/00 , H01L21/66 , G03F7/20
CPC分类号： H01L22/12 , G03F7/70625 , H01L22/20
摘要： Methods and systems are provided for fabricating and measuring features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves fabricating a feature of the semiconductor device structure on a wafer of semiconductor material, determining a hybrid recipe for measuring the feature, configuring a plurality of metrology tools to implement the hybrid recipe, and obtaining a hybrid measurement of the feature in accordance with the hybrid recipe.
摘要翻译：提供了用于制造和测量半导体器件结构的特征的方法和系统。制造半导体器件结构的示例性方法包括在半导体材料的晶片上制造半导体器件结构的特征，确定用于测量特征的混合配方，配置多个计量工具以实现混合配方，以及获得混合根据混合配方测量特征。

5. 发明申请

US20130203188A1 HYBRID METROLOGY FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于半导体器件的混合公式
公开(公告)号：US20130203188A1
公开(公告)日：2013-08-08
申请号：US13365920
申请日：2012-02-03
申请人： Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender Rana
发明人： Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender Rana
IPC分类号： H01L21/66 , G01B21/00
CPC分类号： G01B21/00 , G03F7/70625 , H01L22/12 , H01L22/20
摘要： Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves forming a first feature of the semiconductor device structure on a substrate of semiconductor material, obtaining a first measurement for the semiconductor device structure from a first metrology tool, obtaining a second measurement of the first feature of the semiconductor device structure from a second metrology tool, and determining a hybrid measurement for the first feature based at least in part on the first measurement and the second measurement.
摘要翻译：提供了用于制造和测量半导体器件结构的物理特征的方法和系统。制造半导体器件结构的示例性方法包括在半导体材料的衬底上形成半导体器件结构的第一特征，从第一计量工具获得用于半导体器件结构的第一测量，获得第一特征的第一测量来自第二测量工具的半导体器件结构，以及至少部分地基于第一测量和第二测量来确定第一特征的混合测量。

6. 发明申请

US20130200501A1 IN-SITU ACTIVE WAFER CHARGE SCREENING BY CONFORMAL GROUNDING 审中-公开
标题翻译：通过合理接地的现场有源波形充电屏蔽
公开(公告)号：US20130200501A1
公开(公告)日：2013-08-08
申请号：US13368630
申请日：2012-02-08
申请人： Cheng Cen , Steven B. Herschbein , Narender Rana , Nedal R. Saleh , Alok Vaid
发明人： Cheng Cen , Steven B. Herschbein , Narender Rana , Nedal R. Saleh , Alok Vaid
IPC分类号： H01L21/326 , H01L29/02
CPC分类号： H01L21/326 , H01J2237/0044 , H01J2237/2817 , H01L29/0607
摘要： Embodiments of the invention relate generally to semiconductor wafer technology and, more particularly, to the use of conformal grounding for active charge screening on wafers during wafer processing and metrology. A first aspect of the invention provides a method of reducing an accumulated surface charge on a semiconductor wafer, the method comprising: grounding a layer of conductive material adjacent a substrate of the wafer; and allowing a mirrored charge substantially equal in magnitude and opposite in sign to the accumulated surface charge to be induced along the conductive material.
摘要翻译：本发明的实施例大体上涉及半导体晶片技术，更具体地，涉及在晶片处理和测量期间使用用于在晶片上进行有源电荷屏蔽的保形接地。本发明的第一方面提供了一种减少半导体晶片上累积的表面电荷的方法，所述方法包括：使邻近晶片衬底的导电材料层接地; 并且允许在幅度上基本相等并且符号相反的镜像电荷与沿导电材料诱导的累积表面电荷。

7. 发明申请

US20090228132A1 METHOD AND APPARATUS FOR CONTROLLING STRESSED LAYER GATE PROXIMITY 审中-公开
标题翻译：用于控制受力层门槛的方法和装置
公开(公告)号：US20090228132A1
公开(公告)日：2009-09-10
申请号：US12045081
申请日：2008-03-10
申请人： Kevin R. Lensing , Alok Vaid , Rohit Pal
发明人： Kevin R. Lensing , Alok Vaid , Rohit Pal
IPC分类号： G06F17/00
CPC分类号： H01L22/12 , H01L22/20 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method includes receiving a performance distribution for a plurality of devices to be fabricated in a semiconductor process flow. A performance target for a particular device is specified based on the performance distribution. A stressed material is formed in a recess adjacent a gate electrode of a transistor in the particular device in accordance with at least one operating recipe. The recess is spaced from the gate electrode by a gate proximity distance. A target value for the gate proximity distance is determined based on the performance target. At least one parameter of the operating recipe is determined based on the target value for the gate proximity distance.
摘要翻译：一种方法包括接收要在半导体工艺流程中制造的多个器件的性能分布。基于性能分布指定特定设备的性能目标。根据至少一个操作配方，在与特定装置中的晶体管的栅电极相邻的凹部中形成应力材料。凹槽与栅电极隔开一个栅极接近距离。基于性能目标确定门接近距离的目标值。基于门接近距离的目标值确定操作配方的至少一个参数。

8. 发明申请

US20080248598A1 METHOD AND APPARATUS FOR DETERMINING CHARACTERISTICS OF A STRESSED MATERIAL USING SCATTEROMETRY 审中-公开
标题翻译：用于确定应力分布特征的材料的方法和装置
公开(公告)号：US20080248598A1
公开(公告)日：2008-10-09
申请号：US11697955
申请日：2007-04-09
申请人： Rohit Pal , Alok Vaid
发明人： Rohit Pal , Alok Vaid
IPC分类号： H01L21/66 , H01L21/306 , H01L23/58
CPC分类号： H01L22/12
摘要： A method includes illuminating at least a portion of a first grid including a first plurality of stressed material regions formed at least partially in a semiconducting material. Light reflected from the illuminated portion of the first grid is measured to generate a first reflection profile. A characteristic of the first plurality of stressed material regions is determined based on the first reflection profile. A test structure includes a first plurality of stressed material regions recessed with respect to a surface of a semiconductor layer and defining a first grid. A first plurality of exposed portions of the semiconductor layer is disposed between each of the first plurality of stressed material regions.
摘要翻译：一种方法包括照亮包括至少部分地形成在半导体材料中的第一多个应力材料区域的第一栅格的至少一部分。测量从第一格栅的照明部分反射的光以产生第一反射曲线。基于第一反射曲线确定第一多个应力材料区域的特性。测试结构包括相对于半导体层的表面凹陷并限定第一格栅的第一多个应力材料区域。半导体层的第一多个暴露部分设置在第一多个应力材料区域中的每一个之间。

9. 发明授权

US07838308B2 Method of controlling embedded material/gate proximity 有权
标题翻译：控制嵌入材料/栅极接近度的方法
公开(公告)号：US07838308B2
公开(公告)日：2010-11-23
申请号：US12119196
申请日：2008-05-12
申请人： Rohit Pal , David E. Brown , Alok Vaid , Kevin Lensing
发明人： Rohit Pal , David E. Brown , Alok Vaid , Kevin Lensing
IPC分类号： H01L21/00
CPC分类号： H01L29/7848 , H01L22/12 , H01L22/20 , H01L29/66636 , H01L29/78
摘要： A method that includes forming a gate of a semiconductor device on a substrate and forming a recess for an embedded silicon-straining material in source and drain regions for the gate. In this method, a proximity value, which is defined as a distance between the gate and a closest edge of the recess, is controlled by controlling formation of an oxide layer provided beneath the gate. The method can also include feedforward control of process steps in the formation of the recess based upon values measured during the formation of the recess. The method can also apply feedback control to adjust a subsequent recess formation process performed on a subsequent semiconductor device based on the comparison between a measured proximity value and a target proximity value to decrease a difference between a proximity value of the subsequent semiconductor device and the target proximity value.
摘要翻译：一种方法，包括在衬底上形成半导体器件的栅极，并在栅极的源极和漏极区域中形成嵌入的硅应变材料的凹部。在该方法中，通过控制形成在栅极下方的氧化物层来控制被定义为栅极和凹部的最近边缘之间的距离的接近值。该方法还可以包括基于在形成凹部期间测量的值来形成凹部中的工艺步骤的前馈控制。该方法还可以基于测量的接近度值和目标接近值之间的比较来应用反馈控制来调整对随后的半导体器件执行的随后的凹陷形成处理，以减小随后的半导体器件的接近值与目标之间的差异接近值。

10. 发明授权

US07682845B2 Methods for calibrating a process for growing an epitaxial silicon film and methods for growing an epitaxial silicon film 有权
标题翻译：用于校准用于生长外延硅膜的工艺的方法和用于生长外延硅膜的方法
公开(公告)号：US07682845B2
公开(公告)日：2010-03-23
申请号：US11964935
申请日：2007-12-27
申请人： Rohit Pal , Alok Vaid , Kevin Lensing
发明人： Rohit Pal , Alok Vaid , Kevin Lensing
IPC分类号： G01R31/26
CPC分类号： H01L22/12 , C30B25/16 , C30B29/06 , H01L21/02532 , H01L22/20
摘要： Methods are provided for calibrating a process for growing an epitaxial silicon-comprising film and for growing an epitaxial silicon-comprising film. One method comprises epitaxially growing a first silicon-comprising film on a first silicon substrate that has an adjacent non-crystalline-silicon structure that extends from said first silicon substrate. The step of epitaxially growing uses hydrochloric acid provided at a first hydrochloric acid flow rate for a first time period. A morphology of the first film relevant to the adjacent non-crystalline-silicon structure is analyzed and a thickness of the first film is measured. The first flow rate is adjusted to a second flow rate based on the morphology of the first film. The first time period is adjusted to a second time period based on the second flow rate and the thickness. A second silicon-comprising film on a second silicon substrate is epitaxially grown for the second time period using the second flow rate.
摘要翻译：提供了用于校准用于生长外延含硅膜并用于生长外延含硅膜的工艺的方法。一种方法包括在具有从所述第一硅衬底延伸的相邻非晶硅结构的第一硅衬底上外延生长第一含硅膜。外延生长的步骤使用以第一次盐酸流速提供的盐酸第一次。分析与相邻的非晶硅结构相关的第一膜的形态，并测量第一膜的厚度。基于第一膜的形态将第一流量调节到第二流量。基于第二流量和厚度将第一时间段调整到第二时间段。使用第二流量，在第二时间段外延生长第二硅衬底上的第二含硅膜。

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