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1. 发明申请

US20090280579A1 METHOD OF CONTROLLING EMBEDDED MATERIAL/GATE PROXIMITY 有权
标题翻译：控制嵌入材料/栅格近似的方法
公开(公告)号：US20090280579A1
公开(公告)日：2009-11-12
申请号：US12119196
申请日：2008-05-12
申请人： Rohit Pal , David E. Brown , Alok Vaid , Kevin Lensing
发明人： Rohit Pal , David E. Brown , Alok Vaid , Kevin Lensing
IPC分类号： H01L21/66
CPC分类号： H01L29/7848 , H01L22/12 , H01L22/20 , H01L29/66636 , H01L29/78
摘要： A method that includes forming a gate of a semiconductor device on a substrate and forming a recess for an embedded silicon-straining material in source and drain regions for the gate. In this method, a proximity value, which is defined as a distance between the gate and a closest edge of the recess, is controlled by controlling formation of an oxide layer provided beneath the gate. The method can also include feedforward control of process steps in the formation of the recess based upon values measured during the formation of the recess. The method can also apply feedback control to adjust a subsequent recess formation process performed on a subsequent semiconductor device based on the comparison between a measured proximity value and a target proximity value to decrease a difference between a proximity value of the subsequent semiconductor device and the target proximity value.
摘要翻译：一种方法，包括在衬底上形成半导体器件的栅极，并在栅极的源极和漏极区域中形成嵌入的硅应变材料的凹部。在该方法中，通过控制形成在栅极下方的氧化物层来控制被定义为栅极和凹部的最近边缘之间的距离的接近值。该方法还可以包括基于在形成凹部期间测量的值来形成凹部中的工艺步骤的前馈控制。该方法还可以基于测量的接近度值和目标接近值之间的比较来应用反馈控制来调整对随后的半导体器件执行的随后的凹陷形成处理，以减小随后的半导体器件的接近值与目标之间的差异接近值。

2. 发明授权

US07838308B2 Method of controlling embedded material/gate proximity 有权
标题翻译：控制嵌入材料/栅极接近度的方法
公开(公告)号：US07838308B2
公开(公告)日：2010-11-23
申请号：US12119196
申请日：2008-05-12
申请人： Rohit Pal , David E. Brown , Alok Vaid , Kevin Lensing
发明人： Rohit Pal , David E. Brown , Alok Vaid , Kevin Lensing
IPC分类号： H01L21/00
CPC分类号： H01L29/7848 , H01L22/12 , H01L22/20 , H01L29/66636 , H01L29/78
摘要： A method that includes forming a gate of a semiconductor device on a substrate and forming a recess for an embedded silicon-straining material in source and drain regions for the gate. In this method, a proximity value, which is defined as a distance between the gate and a closest edge of the recess, is controlled by controlling formation of an oxide layer provided beneath the gate. The method can also include feedforward control of process steps in the formation of the recess based upon values measured during the formation of the recess. The method can also apply feedback control to adjust a subsequent recess formation process performed on a subsequent semiconductor device based on the comparison between a measured proximity value and a target proximity value to decrease a difference between a proximity value of the subsequent semiconductor device and the target proximity value.
摘要翻译：一种方法，包括在衬底上形成半导体器件的栅极，并在栅极的源极和漏极区域中形成嵌入的硅应变材料的凹部。在该方法中，通过控制形成在栅极下方的氧化物层来控制被定义为栅极和凹部的最近边缘之间的距离的接近值。该方法还可以包括基于在形成凹部期间测量的值来形成凹部中的工艺步骤的前馈控制。该方法还可以基于测量的接近度值和目标接近值之间的比较来应用反馈控制来调整对随后的半导体器件执行的随后的凹陷形成处理，以减小随后的半导体器件的接近值与目标之间的差异接近值。

3. 发明授权

US07682845B2 Methods for calibrating a process for growing an epitaxial silicon film and methods for growing an epitaxial silicon film 有权
标题翻译：用于校准用于生长外延硅膜的工艺的方法和用于生长外延硅膜的方法
公开(公告)号：US07682845B2
公开(公告)日：2010-03-23
申请号：US11964935
申请日：2007-12-27
申请人： Rohit Pal , Alok Vaid , Kevin Lensing
发明人： Rohit Pal , Alok Vaid , Kevin Lensing
IPC分类号： G01R31/26
CPC分类号： H01L22/12 , C30B25/16 , C30B29/06 , H01L21/02532 , H01L22/20
摘要： Methods are provided for calibrating a process for growing an epitaxial silicon-comprising film and for growing an epitaxial silicon-comprising film. One method comprises epitaxially growing a first silicon-comprising film on a first silicon substrate that has an adjacent non-crystalline-silicon structure that extends from said first silicon substrate. The step of epitaxially growing uses hydrochloric acid provided at a first hydrochloric acid flow rate for a first time period. A morphology of the first film relevant to the adjacent non-crystalline-silicon structure is analyzed and a thickness of the first film is measured. The first flow rate is adjusted to a second flow rate based on the morphology of the first film. The first time period is adjusted to a second time period based on the second flow rate and the thickness. A second silicon-comprising film on a second silicon substrate is epitaxially grown for the second time period using the second flow rate.
摘要翻译：提供了用于校准用于生长外延含硅膜并用于生长外延含硅膜的工艺的方法。一种方法包括在具有从所述第一硅衬底延伸的相邻非晶硅结构的第一硅衬底上外延生长第一含硅膜。外延生长的步骤使用以第一次盐酸流速提供的盐酸第一次。分析与相邻的非晶硅结构相关的第一膜的形态，并测量第一膜的厚度。基于第一膜的形态将第一流量调节到第二流量。基于第二流量和厚度将第一时间段调整到第二时间段。使用第二流量，在第二时间段外延生长第二硅衬底上的第二含硅膜。

4. 发明申请

US20080248598A1 METHOD AND APPARATUS FOR DETERMINING CHARACTERISTICS OF A STRESSED MATERIAL USING SCATTEROMETRY 审中-公开
标题翻译：用于确定应力分布特征的材料的方法和装置
公开(公告)号：US20080248598A1
公开(公告)日：2008-10-09
申请号：US11697955
申请日：2007-04-09
申请人： Rohit Pal , Alok Vaid
发明人： Rohit Pal , Alok Vaid
IPC分类号： H01L21/66 , H01L21/306 , H01L23/58
CPC分类号： H01L22/12
摘要： A method includes illuminating at least a portion of a first grid including a first plurality of stressed material regions formed at least partially in a semiconducting material. Light reflected from the illuminated portion of the first grid is measured to generate a first reflection profile. A characteristic of the first plurality of stressed material regions is determined based on the first reflection profile. A test structure includes a first plurality of stressed material regions recessed with respect to a surface of a semiconductor layer and defining a first grid. A first plurality of exposed portions of the semiconductor layer is disposed between each of the first plurality of stressed material regions.
摘要翻译：一种方法包括照亮包括至少部分地形成在半导体材料中的第一多个应力材料区域的第一栅格的至少一部分。测量从第一格栅的照明部分反射的光以产生第一反射曲线。基于第一反射曲线确定第一多个应力材料区域的特性。测试结构包括相对于半导体层的表面凹陷并限定第一格栅的第一多个应力材料区域。半导体层的第一多个暴露部分设置在第一多个应力材料区域中的每一个之间。

5. 发明申请

US20090228132A1 METHOD AND APPARATUS FOR CONTROLLING STRESSED LAYER GATE PROXIMITY 审中-公开
标题翻译：用于控制受力层门槛的方法和装置
公开(公告)号：US20090228132A1
公开(公告)日：2009-09-10
申请号：US12045081
申请日：2008-03-10
申请人： Kevin R. Lensing , Alok Vaid , Rohit Pal
发明人： Kevin R. Lensing , Alok Vaid , Rohit Pal
IPC分类号： G06F17/00
CPC分类号： H01L22/12 , H01L22/20 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method includes receiving a performance distribution for a plurality of devices to be fabricated in a semiconductor process flow. A performance target for a particular device is specified based on the performance distribution. A stressed material is formed in a recess adjacent a gate electrode of a transistor in the particular device in accordance with at least one operating recipe. The recess is spaced from the gate electrode by a gate proximity distance. A target value for the gate proximity distance is determined based on the performance target. At least one parameter of the operating recipe is determined based on the target value for the gate proximity distance.
摘要翻译：一种方法包括接收要在半导体工艺流程中制造的多个器件的性能分布。基于性能分布指定特定设备的性能目标。根据至少一个操作配方，在与特定装置中的晶体管的栅电极相邻的凹部中形成应力材料。凹槽与栅电极隔开一个栅极接近距离。基于性能目标确定门接近距离的目标值。基于门接近距离的目标值确定操作配方的至少一个参数。

6. 发明授权

US08664057B2 High-K metal gate electrode structures formed by early cap layer adaptation 有权
标题翻译：通过早期盖层适应形成的高K金属栅电极结构
公开(公告)号：US08664057B2
公开(公告)日：2014-03-04
申请号：US13565970
申请日：2012-08-03
申请人： Rohit Pal , Sven Beyer , Andy Wei , Richard Carter
发明人： Rohit Pal , Sven Beyer , Andy Wei , Richard Carter
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763 , H01L21/336 , H01L21/28 , H01L21/44 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828
摘要： When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.
摘要翻译：当在不同导电类型的晶体管中形成高k金属栅极电极结构时，同时在一种类型的晶体管中选择性地并入嵌入式应变诱导半导体合金，可以通过选择性地减小介电帽材料的厚度来实现优异的工艺均匀性栅极层堆叠在不接收应变诱导半导体合金的晶体管的有源区上方。在这种情况下，可以在早期制造阶段中形成复杂的高k金属栅极电极结构的工艺策略中实现优异的限制和因此敏感栅极材料的完整性，而在替代栅极方法中，优良的工艺均匀性是在暴露观察者电极材料的表面时实现。

7. 发明授权

US08373228B2 Semiconductor transistor device structure with back side source/drain contact plugs, and related manufacturing method 有权
标题翻译：具有背面源极/漏极接触插头的半导体晶体管器件结构及相关制造方法
公开(公告)号：US08373228B2
公开(公告)日：2013-02-12
申请号：US12687607
申请日：2010-01-14
申请人： Bin Yang , Rohit Pal , Michael Hargrove
发明人： Bin Yang , Rohit Pal , Michael Hargrove
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/845 , H01L23/485 , H01L27/12 , H01L27/1211
摘要： A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.
摘要翻译：此处提供制造具有背面导电插头的半导体器件的方法。该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

8. 发明申请

US20130032893A1 SEMICONDUCTOR DEVICE COMPRISING METAL GATE ELECTRODE STRUCTURES AND NON-FETS WITH DIFFERENT HEIGHT BY EARLY ADAPTATION OF GATE STACK TOPOGRAPHY 审中-公开
标题翻译：包含金属栅极电极结构和不同高度的非FET的半导体器件通过栅格堆叠拓扑的早期适应
公开(公告)号：US20130032893A1
公开(公告)日：2013-02-07
申请号：US13550693
申请日：2012-07-17
申请人： Rohit Pal , George Mulfinger
发明人： Rohit Pal , George Mulfinger
IPC分类号： H01L27/088 , H01L21/283
CPC分类号： H01L23/5256 , H01L23/485 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： Gate height scaling in sophisticated semiconductor devices may be implemented without requiring a redesign of non-transistor devices. To this end, the semiconductor electrode material may be adapted in its thickness above active regions and isolation regions that receive the non-transistor devices. Thereafter, the actual patterning of the adapted gate layer stack may be performed so as to obtain gate electrode structures of a desired height for improving, in particular, AC performance without requiring a redesign of the non-transistor devices.
摘要翻译：可以实现复杂半导体器件中的栅极高度缩放，而不需要重新设计非晶体管器件。为此，可以将半导体电极材料的厚度适用于有源区域和接收非晶体管器件的隔离区域。此后，可以执行适合的栅极层堆叠的实际图案化，以获得所需高度的栅电极结构，以改善特别是AC性能，而不需要重新设计非晶体管器件。

9. 发明申请

US20120295420A1 SEMICONDUCTOR DEVICES WITH REDUCED STI TOPOGRAPHY BY USING CHEMICAL OXIDE REMOVAL 审中-公开
标题翻译：通过使用化学氧化物去除减少STI天文的半导体器件
公开(公告)号：US20120295420A1
公开(公告)日：2012-11-22
申请号：US13470906
申请日：2012-05-14
申请人： Rohit Pal , Stephan-Detlef Kronholz
发明人： Rohit Pal , Stephan-Detlef Kronholz
IPC分类号： H01L21/20 , H01L21/283
CPC分类号： H01L21/76224 , H01L21/02057 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L29/66651 , H01L29/7833
摘要： A thermal oxide may be removed in semiconductor devices prior to performing complex manufacturing processes, such as forming sophisticated gate electrode structures, by using a gaseous process atmosphere instead of a wet chemical etch process, wherein the masking of specific device regions may be accomplished on the basis of a resist mask.
摘要翻译：在通过使用气体处理气氛而不是湿式化学蚀刻工艺执行复杂的制造工艺（例如形成复杂的栅电极结构）之前，可以在半导体器件中去除热氧化物，其中特定器件区域的掩蔽可以在抗蚀剂掩模的基础。

10. 发明申请

US20120193727A1 ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION 有权
标题翻译：通过扩大栅极电介质层材料来调节放电晶体管的栅极电压以进行电介质稳定化
公开(公告)号：US20120193727A1
公开(公告)日：2012-08-02
申请号：US13444955
申请日：2012-04-12
申请人： Richard Carter , Martin Trentzsch , Sven Beyer , Rohit Pal
发明人： Richard Carter , Martin Trentzsch , Sven Beyer , Rohit Pal
IPC分类号： H01L27/088
CPC分类号： H01L21/823462 , H01L21/28176 , H01L21/28194 , H01L29/513 , H01L29/517
摘要： Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.
摘要翻译：复杂的栅极电极结构可以通过在进行用于稳定敏感栅极介电材料的处理之前提供包括可能扩散到栅极电介质材料中的所需物质的覆盖层来形成。以这种方式，与常规策略相比，可以基于用于阈值调节物质的降低的温度和剂量来形成复杂的高k金属栅电极结构。此外，可以为两种类型的晶体管沉积单个含金属的电极材料。

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