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1. 发明申请

US20130245806A1 AUTOMATED HYBRID METROLOGY FOR SEMICONDUCTOR DEVICE FABRICATION 有权
标题翻译：用于半导体器件制造的自动化混合规格
公开(公告)号：US20130245806A1
公开(公告)日：2013-09-19
申请号：US13419286
申请日：2012-03-13
申请人： Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender N. Rana
发明人： Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender N. Rana
IPC分类号： G06F19/00
CPC分类号： H01L22/12 , G03F7/70625 , H01L22/20
摘要： Methods and systems are provided for fabricating and measuring features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves fabricating a feature of the semiconductor device structure on a wafer of semiconductor material, determining a hybrid recipe for measuring the feature, configuring a plurality of metrology tools to implement the hybrid recipe; and obtaining a hybrid measurement of the feature in accordance with the hybrid recipe.
摘要翻译：提供了用于制造和测量半导体器件结构的特征的方法和系统。制造半导体器件结构的示例性方法包括在半导体材料的晶片上制造半导体器件结构的特征，确定用于测量特征的混合配方，配置多个计量工具以实现混合配方; 以及根据所述混合配方获得所述特征的混合测量。

2. 发明授权

US07107177B2 Combining multiple reference measurement collections into a weighted reference measurement collection 失效
标题翻译：将多个参考测量集合组合到加权参考测量集合中
公开(公告)号：US07107177B2
公开(公告)日：2006-09-12
申请号：US10906310
申请日：2005-02-14
申请人： Matthew J. Sendelbach
发明人： Matthew J. Sendelbach
IPC分类号： G01D1/00 , G06F15/00
CPC分类号： G01D1/02
摘要： Combining of reference measurement collections (RMCs) of at least three reference measurement systems into a weighted reference measurement collection (wRMC) is disclosed. Each RMC includes a plurality of corresponding sample measurements, each of which has a measurement value of the same sample. The invention plots corresponding measurement values to generate a plurality of data pairs for each possible RMC pairing. A best-fit line of the plurality of data pairs for each RMC pairing is then generated, and a residual for each data pair is calculated. A weight is then assigned to each sample measurement for each RMC based on the residuals associated with a respective RMC to which the sample measurement belongs, favoring a smaller residual more than a larger residual. A weighted reference measurement is then generated based on the weights, and the measurement value for the respective sample measurement for each RMC.
摘要翻译：公开了将至少三个参考测量系统的参考测量集合（RMC）组合到加权参考测量集合（wRMC）中。每个RMC包括多个对应的样本测量值，每个测量值具有相同样本的测量值。本发明绘出相应的测量值以产生用于每个可能的RMC配对的多个数据对。然后生成用于每个RMC配对的多个数据对的最佳拟合线，并且计算每个数据对的残差。然后根据与样本测量所属的相应RMC相关联的残差，将权重分配给每个RMC的每个样本测量，有利于比较大残差更小的残差。然后基于权重和每个RMC的各个样本测量的测量值生成加权参考测量。

3. 发明授权

US07791723B2 Optical measurement using fixed polarizer 有权
标题翻译：使用固定偏光镜进行光学测量
公开(公告)号：US07791723B2
公开(公告)日：2010-09-07
申请号：US12017151
申请日：2008-01-21
申请人： Charles N. Archie , Matthew J. Sendelbach , Shahin Zangooie
发明人： Charles N. Archie , Matthew J. Sendelbach , Shahin Zangooie
IPC分类号： G01N4/00
CPC分类号： G01N21/21
摘要： Optical measurement method and systems employing a fixed polarizer are disclosed. In one embodiment, the method includes providing at least one optical detection system having a fixed polarizer having a first type polarization; providing a first target on a substrate and a second target on the substrate; optically measuring the first target and the second target using the at least one optical detection system with the first target being positioned at a right angle relative to the second target to obtain a first measurement with the first type polarization and a second measurement with a second type-equivalent polarization; and combining the first measurement and the second measurement to obtain the optical measurement.
摘要翻译：公开了使用固定偏振器的光学测量方法和系统。在一个实施例中，该方法包括提供至少一个光学检测系统，其具有具有第一类型偏振的固定偏振器; 在衬底上提供第一靶和在衬底上提供第二靶; 使用所述至少一个光学检测系统光学测量第一目标和第二目标，其中第一目标相对于第二目标定位成直角，以获得具有第一类型偏振的第一测量和具有第二类型的第二测量等效极化并结合第一测量和第二测量以获得光学测量。

4. 发明授权

US08157978B2 Etching system and method for forming multiple porous semiconductor regions with different optical and structural properties on a single semiconductor wafer 有权
标题翻译：用于在单个半导体晶片上形成具有不同光学和结构特性的多个多孔半导体区域的蚀刻系统和方法
公开(公告)号：US08157978B2
公开(公告)日：2012-04-17
申请号：US12361736
申请日：2009-01-29
申请人： Matthew J. Sendelbach , Alok Vaid , Shahin Zangooie
发明人： Matthew J. Sendelbach , Alok Vaid , Shahin Zangooie
IPC分类号： C25D5/02 , C25D17/00
CPC分类号： C25F7/00 , C25F3/12 , C25F3/14 , H01L21/3063
摘要： Disclosed is an electrochemical etching system with localized etching capability. The system allows multiple different porous semiconductor regions to be formed on a single semiconductor wafer. Localized etching is achieved through the use of one or more stationary and/or movable computer-controlled inner containers operating within an outer container. The outer container holds the electrolyte solution and acts as an electrolyte supply source for the inner container(s). The inner container(s) limit the size of the etched region of the semiconductor wafer by confining the electric field. Additionally, the current amount passing through each inner container during the electrochemical etching process can be selectively adjusted to achieve a desired result within the etched region. Localized etching of sub-regions within each etched region can also be achieved through the use of different stationary and/or moveable electrode structures and shields within each inner container. Also disclosed are associated method embodiments.
摘要翻译：公开了具有局部蚀刻能力的电化学蚀刻系统。该系统允许在单个半导体晶片上形成多个不同的多孔半导体区域。通过使用在外部容器内操作的一个或多个固定和/或可移动计算机控制的内部容器来实现局部蚀刻。外部容器保持电解质溶液并用作内部容器的电解质供应源。内部容器通过限制电场来限制半导体晶片的蚀刻区域的尺寸。此外，可以选择性地调节在电化学蚀刻工艺期间通过每个内部容器的电流量，以在蚀刻区域内实现期望的结果。每个蚀刻区域内的子区域的局部蚀刻也可以通过在每个内部容器内使用不同的固定和/或可移动的电极结构和屏蔽来实现。还公开了相关联的方法实施例。

5. 发明授权

US6066566A High selectivity collar oxide etch processes 失效
标题翻译：高选择性环氧化物蚀刻工艺
公开(公告)号：US6066566A
公开(公告)日：2000-05-23
申请号：US14805
申请日：1998-01-28
申请人： Munir-ud-Din Naeem , Matthew J. Sendelbach , Ting-Hao Wang
发明人： Munir-ud-Din Naeem , Matthew J. Sendelbach , Ting-Hao Wang
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/334 , H01L21/8242 , H01L27/108 , H01L21/00
CPC分类号： H01L27/10861 , H01L29/66181
摘要： A collar oxide is formed in a provided a semiconductor substrate having (3) a partially full trench, (2) (i) fill surface defined by fill material partially filling said trench, (ii) upper surface outside of said trench, and (iii) trench sidewall surface not covered by said fill material, and (3) a conformal oxide layer overlying said fill, upper, and sidewall surfaces, by selectively etching as follows:(a) contacting the substrate with a mixture of hydrogen-containing fluorocarbon and an oxygen source under reactive ion etching conditions until at least a portion of the conformal oxide layer on the upper surface is removed, and(b) contacting the substrate from step (a) with a mixture of a hydrogen-free fluorocarbon and a diluent gas under reactive ion etching conditions to further remove conformal oxide remaining on the fill surface and to overetch the upper and fill surfaces, whereby a substantial portion of conformal oxide remains on the side walls to form the collar oxide.A further step (c) may be added after the overetching to remove any residual byproduct polymer deposits. The methods are especially adapted for use in the manufacture of high aspect ratio trench capacitors for integrated circuits. The method provides reduced degradation of pad nitride layers and may be conducted without the use of CO gas.
摘要翻译：在所提供的半导体衬底中形成环状氧化物，其具有（3）部分全沟槽，（2）（i）由部分填充所述沟槽的填充材料限定的填充表面，（ii）所述沟槽外部的上表面，和（iii））沟槽侧壁表面，以及（3）通过如下选择性蚀刻来覆盖所述填充物，上侧壁和侧壁表面的共形氧化物层：（a）使基底与含氢碳氟化合物的混合物和在反应离子蚀刻条件下的氧源，直到去除上表面上的共形氧化物层的至少一部分，和（b）使来自步骤（a）的基底与无氢氟碳化合物和稀释气体的混合物在反应离子蚀刻条件下，以进一步除去残留在填充表面上的保形氧化物，并且去除上表面和填充表面，由此大部分共形氧化物残留在侧壁上以形成环氧化物。在过蚀刻之后可以加入另外的步骤（c）以除去任何残留的副产物聚合物沉积物。该方法特别适用于制造用于集成电路的高宽比沟槽电容器。该方法提供了氮化物层的降低的降低，并且可以在不使用CO气体的情况下进行。

6. 发明授权

US07760360B2 Monitoring a photolithographic process using a scatterometry target 失效
标题翻译：使用散射仪目标监控光刻工艺
公开(公告)号：US07760360B2
公开(公告)日：2010-07-20
申请号：US11820305
申请日：2007-06-18
申请人： Charles N. Archie , Matthew J. Sendelbach
发明人： Charles N. Archie , Matthew J. Sendelbach
IPC分类号： G01N21/55 , G01B11/14 , G03F9/00 , G03C5/00 , G03B27/32
CPC分类号： G03F7/70641 , G03F7/70683 , H01L22/34
摘要： A method is provided for monitoring a photolithographic process in which a substrate is patterned to form (i) a scatterometry target having a plurality of parallel elongated features, and desirably, (ii) other features each having at least one of a microelectronic function or a micro-electromechanical function. Desirably, each elongated feature of the scatterometry target has a length in a lengthwise direction and a plurality of stress-relief features disposed at a plurality of positions along the length of each elongated feature. A return signal is detected in response to illumination of the scatterometry target. The return signal can be used to determine a result of the photolithographic process.
摘要翻译：提供了一种用于监测光刻工艺的方法，其中衬底被图案化以形成（i）具有多个平行细长特征的散射仪，并且期望地，（ii）其他特征，每个具有微电子功能或微机电功能。期望地，散射测量目标的每个细长特征具有沿长度方向的长度，并且多个应力消除特征设置在沿着每个细长特征的长度的多个位置处。响应于散射仪的照明来检测返回信号。返回信号可用于确定光刻工艺的结果。

7. 发明申请

US20080158564A1 Monitoring a photolithographic process using a scatterometry target 失效
标题翻译：使用散射仪目标监控光刻工艺
公开(公告)号：US20080158564A1
公开(公告)日：2008-07-03
申请号：US11820305
申请日：2007-06-18
申请人： Charles N. Archie , Matthew J. Sendelbach
发明人： Charles N. Archie , Matthew J. Sendelbach
IPC分类号： G01N21/55
CPC分类号： G03F7/70641 , G03F7/70683 , H01L22/34
摘要： A method is provided for monitoring a photolithographic process in which a substrate is patterned to form (i) a scatterometry target having a plurality of parallel elongated features, and desirably, (ii) other features each having at least one of a microelectronic function or a micro-electromechanical function. Desirably, each elongated feature of the scatterometry target has a length in a lengthwise direction and a plurality of stress-relief features disposed at a plurality of positions along the length of each elongated feature. A return signal is detected in response to illumination of the scatterometry target. The return signal can be used to determine a result of the photolithographic process.
摘要翻译：提供了一种用于监测光刻工艺的方法，其中衬底被图案化以形成（i）具有多个平行细长特征的散射仪，并且期望地，（ii）其他特征，每个具有微电子功能或微机电功能。期望地，散射测量目标的每个细长特征具有沿长度方向的长度，并且多个应力消除特征设置在沿着每个细长特征的长度的多个位置处。响应于散射仪的照明来检测返回信号。返回信号可用于确定光刻工艺的结果。

8. 发明申请

US20080151268A1 ASSESSMENT AND OPTIMIZATION FOR METROLOGY INSTRUMENT INCLUDING UNCERTAINTY OF TOTAL MEASUREMENT UNCERTAINTY 失效
标题翻译：量测仪器的评估和优化，包括总测量不确定度的不确定性
公开(公告)号：US20080151268A1
公开(公告)日：2008-06-26
申请号：US11866449
申请日：2007-10-03
申请人： Charles N. Archie , G. William Banker , Matthew J. Sendelbach
发明人： Charles N. Archie , G. William Banker , Matthew J. Sendelbach
IPC分类号： G01B11/14
CPC分类号： G03F7/70616 , G01B21/045 , G03F7/70483 , H01L22/12
摘要： Methods and related program product for assessing and optimizing metrology instruments by determining a total measurement uncertainty (TMU) based on precision and accuracy. The TMU is calculated based on a linear regression analysis and removing a reference measuring system uncertainty (URMS) from a net residual error. The TMU provides an objective and more accurate representation of whether a measurement system under test has an ability to sense true product variation. The invention also includes a method for determining an uncertainty of the TMU.
摘要翻译：通过基于精度和精度确定总测量不确定度（TMU）来评估和优化计量仪器的方法和相关程序产品。 TMU是基于线性回归分析计算的，并从净残差误差去除参考测量系统不确定度（U RMS）。 TMU提供了客观和更准确的表示，测试中的测量系统是否具有感测真实产品变化的能力。本发明还包括一种用于确定TMU的不确定性的方法。

9. 发明授权

US09330985B2 Automated hybrid metrology for semiconductor device fabrication 有权
标题翻译：用于半导体器件制造的自动混合测量
公开(公告)号：US09330985B2
公开(公告)日：2016-05-03
申请号：US13419286
申请日：2012-03-13
申请人： Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender N. Rana
发明人： Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender N. Rana
IPC分类号： G06F19/00 , H01L21/66 , G03F7/20
CPC分类号： H01L22/12 , G03F7/70625 , H01L22/20
摘要： Methods and systems are provided for fabricating and measuring features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves fabricating a feature of the semiconductor device structure on a wafer of semiconductor material, determining a hybrid recipe for measuring the feature, configuring a plurality of metrology tools to implement the hybrid recipe, and obtaining a hybrid measurement of the feature in accordance with the hybrid recipe.
摘要翻译：提供了用于制造和测量半导体器件结构的特征的方法和系统。制造半导体器件结构的示例性方法包括在半导体材料的晶片上制造半导体器件结构的特征，确定用于测量特征的混合配方，配置多个计量工具以实现混合配方，以及获得混合根据混合配方测量特征。

10. 发明申请

US20130203188A1 HYBRID METROLOGY FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于半导体器件的混合公式
公开(公告)号：US20130203188A1
公开(公告)日：2013-08-08
申请号：US13365920
申请日：2012-02-03
申请人： Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender Rana
发明人： Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender Rana
IPC分类号： H01L21/66 , G01B21/00
CPC分类号： G01B21/00 , G03F7/70625 , H01L22/12 , H01L22/20
摘要： Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves forming a first feature of the semiconductor device structure on a substrate of semiconductor material, obtaining a first measurement for the semiconductor device structure from a first metrology tool, obtaining a second measurement of the first feature of the semiconductor device structure from a second metrology tool, and determining a hybrid measurement for the first feature based at least in part on the first measurement and the second measurement.
摘要翻译：提供了用于制造和测量半导体器件结构的物理特征的方法和系统。制造半导体器件结构的示例性方法包括在半导体材料的衬底上形成半导体器件结构的第一特征，从第一计量工具获得用于半导体器件结构的第一测量，获得第一特征的第一测量来自第二测量工具的半导体器件结构，以及至少部分地基于第一测量和第二测量来确定第一特征的混合测量。

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