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1. 发明授权

US07106643B2 Method for manufacturing memory device provided with a defect recovery mechanism featuring a redundancy circuit 失效
标题翻译：一种具有冗余电路的缺陷恢复机构的存储装置的制造方法
公开(公告)号：US07106643B2
公开(公告)日：2006-09-12
申请号：US11139513
申请日：2005-05-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C29/04 , G11C29/18 , G11C29/24 , G11C8/12
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： Method for manufacturing a memory device, the memory being a memory array with a spare bit line and being provided with a defect recovery scheme featuring a redundancy circuit. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
摘要翻译：用于制造存储器件的方法，所述存储器是具有备用位线的存储器阵列，并且提供具有冗余电路的缺陷恢复方案。冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。在此比较的基础上，进行适当的缺陷恢复。

2. 发明授权

US06909647B2 Semiconductor device having redundancy circuit 失效
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US06909647B2
公开(公告)日：2005-06-21
申请号：US10813240
申请日：2004-03-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
摘要翻译：半导体存储器具有冗余电路的缺陷恢复方案。存储器中的存储器阵列具有多个字线，多个位线，备用位线和多个存储器单元。冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。在此比较的基础上，进行适当的缺陷恢复。

3. 发明授权

US06577544B2 Semiconductor device having redundancy circuit 失效
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US06577544B2
公开(公告)日：2003-06-10
申请号：US09992001
申请日：2001-11-26
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
摘要翻译：半导体存储器具有冗余电路的缺陷恢复方案。存储器中的存储器阵列具有多个字线，多个位线，备用位线和多个存储器单元。冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。在此比较的基础上，进行适当的缺陷恢复。

4. 发明授权

US5815448A Semiconductor memory having redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器
公开(公告)号：US5815448A
公开(公告)日：1998-09-29
申请号：US825605
申请日：1997-03-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a dynamic random access memory (DRAM) having a storage capacity of 16 mega bits or more. In such a DRAM, the memory array is divided into memory mats. According to the present redundancy technique, for a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, memory cells disposed at desired ones of the two-level crossings, and spare bit lines, there is provided a redundancy circuit having a memory for storing therein a defective address existing in the memory array and comparing an address to be accessed with the stored defective address, and selection circuitry including logical OR gates for replacing a defective bit line by a spare bit line in accordance with the result of the comparison. Each of the address comparing circuits has stored therein the column address of a defective bit line and a part of the row address indicating the memory mat corresponding to the defective bit line.
摘要翻译：引入冗余技术用于半导体存储器，更具体地，涉及具有16兆位或更多存储容量的动态随机存取存储器（DRAM）的冗余技术。在这样的DRAM中，存储器阵列被分成存储器垫。根据本技术的冗余技术，对于包含具有多个字线的存储器阵列的半导体存储器，配置成在字线和位线之间形成2级交叉的多位位线，位于提供了两级交叉中的期望的和备用位线，提供了一种冗余电路，其具有用于在其中存储存在于存储器阵列中的缺陷地址并将要访问的地址与所存储的缺陷地址进行比较的存储器，以及选择电路包括用于根据比较结果用备用位线替换有缺陷位线的逻辑“或”门。每个地址比较电路在其中存储有缺陷位线的列地址和指示与有缺陷位线对应的存储器堆的行地址的一部分。

5. 发明授权

US5402376A Semiconductor memory having redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器
公开(公告)号：US5402376A
公开(公告)日：1995-03-28
申请号：US103781
申请日：1993-08-10
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
IPC分类号： G11C11/413 , G11C5/14 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/83 , G11C29/832 , G11C5/14
摘要： In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.
摘要翻译：在半导体存储器中，提供开关电路，以便当需要时，禁止向每个正常存储器块提供电压和信号。另一方面，在半导体存储器处于待机模式时，在芯片上提供ROM以存储消耗过大待机电流的缺陷存储块的地址。开关电路由ROM的输出控制，以便阻止向缺陷存储器块提供电压和信号。然后，代替有缺陷的正常存储块的备用存储块接收电压和信号供应。

6. 发明授权

US5265055A Semiconductor memory having redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器
公开(公告)号：US5265055A
公开(公告)日：1993-11-23
申请号：US818434
申请日：1991-12-27
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/80 , G11C29/808 , G11C29/781
摘要： A redundancy technique is introduced for a semiconductor memory and, more particularly a redundancy technique for a dynamic random access memory (DRAM) having a storage capacity of 16 mega bits or more. In such a DRAM, the efficiency of the redundancy technique is reduced, since a memory array is divided into a large number of memory mats. According to the present redundancy technique, in a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, and memory cells disposed at desired ones of the two-level crossings, there is provided, furthermore, a plurality of spare word (or bit) lines, address comparing circuits for storing therein a defective address existing in the memory array, to compare an address to be accessed with the defective address, and selection circuitry for replacing a word or bit line including a defective memory cell by a spare word (or bit) line in accordance with the result of the comparison. The memory array of the semiconductor memory is divided into M memory mats (where M .gtoreq.2), the number m of word or bit lines which are simultaneously replaced by spare word (or bit) lines, is less than the number M and equal to a divisor thereof, and the number L of spare word (or bit) lines per one memory mat and the number R of address comparing circuits satisfy a relation L
摘要翻译：为半导体存储器引入冗余技术，更具体地说，涉及具有16兆位或更多存储容量的动态随机存取存储器（DRAM）的冗余技术。在这样的DRAM中，冗余技术的效率降低，因为存储器阵列被分成大量的存储器垫。根据本冗余技术，在包括具有多个字线的存储器阵列的半导体存储器中，布置成使得在字线和位线之间形成两级交叉的多个位线，并且设置存储单元此外，在两级交叉口中的期望的一个处，还提供了多个备用字（或位）线，地址比较电路，用于在其中存储存在存储器阵列中的缺陷地址，以将要访问的地址与缺陷地址和用于根据比较结果用备用字（或位）行替换包括有缺陷存储单元的字或位线的选择电路。半导体存储器的存储器阵列被分成M个存储器垫（其中M> / = 2），由备用字（或位）线同时替换的字或位线的数量m小于数M，每个存储器垫的备用字（或位）的数量L和地址比较电路的数量R满足L

7. 发明申请

US20050219922A1 Semiconductor device having redundancy circuit 失效
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US20050219922A1
公开(公告)日：2005-10-06
申请号：US11139513
申请日：2005-05-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： Method for manufacturing a memory device, the memory being a memory array with a spare bit line and being provided with a defect recovery scheme featuring a redundancy circuit. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
摘要翻译：用于制造存储器件的方法，所述存储器是具有备用位线的存储器阵列，并且提供具有冗余电路的缺陷恢复方案。冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。在此比较的基础上，进行适当的缺陷恢复。

8. 发明授权

US5179539A Large scale integrated circuit having low internal operating voltage 失效
标题翻译：具有低内部工作电压的大规模集成电路
公开(公告)号：US5179539A
公开(公告)日：1993-01-12
申请号：US865677
申请日：1992-04-08
申请人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
发明人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/4074 , H01L27/02
CPC分类号： G11C5/147 , G05F1/465 , G05F3/245 , G05F3/247 , G11C11/4074 , H01L27/0203
摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
摘要翻译：涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。提供了改进的测试这些电路的方法。

9. 发明授权

US06754114B2 Semiconductor device having redundancy circuit 失效
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US06754114B2
公开(公告)日：2004-06-22
申请号：US10401975
申请日：2003-03-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
摘要翻译：半导体存储器具有冗余电路的缺陷恢复方案。存储器中的存储器阵列具有多个字线，多个位线，备用位线和多个存储器单元。冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。在此比较的基础上，进行适当的缺陷恢复。

10. 发明授权

US5966336A Semiconductor device having redundancy circuit 有权
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US5966336A
公开(公告)日：1999-10-12
申请号：US144258
申请日：1998-08-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a memory, for example, a dynamic random access memory (DRAM) having a memory array which is divided into memory mats and a storage capacity of 16 mega bits or more. According to the present redundancy technique, for a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, memory cells disposed at desired ones of the two-level crossings, and spare bit lines, there is provided a redundancy circuit having a memory for storing therein a defective address existing in the memory array and comparing an address to be accessed with the stored defective address. Each of the address comparing circuits has stored therein the column address of a defective bit line and a part of the row address indicating the memory mat corresponding to the defective bit line.
摘要翻译：为半导体存储器引入冗余技术，更具体地说，涉及一种用于存储器的冗余技术，例如具有存储器阵列的动态随机存取存储器（DRAM），该存储器阵列被分成存储器阵列，存储容量为16兆比特或者更多。根据本技术的冗余技术，对于包含具有多个字线的存储器阵列的半导体存储器，配置成在字线和位线之间形成2级交叉的多位位线，位于提供了两级交叉中的期望的和备用位线，提供了一种冗余电路，其具有用于在其中存储存在于存储器阵列中的缺陷地址并将要访问的地址与存储的缺陷地址进行比较的存储器。每个地址比较电路在其中存储有缺陷位线的列地址和指示与有缺陷位线对应的存储器堆的行地址的一部分。

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