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1. 发明申请

US20050168245A1 Logical circuit 有权
标题翻译：逻辑电路
公开(公告)号：US20050168245A1
公开(公告)日：2005-08-04
申请号：US11042335
申请日：2005-01-26
申请人： Hiroyuki Kobayashi , Masaki Okuda
发明人： Hiroyuki Kobayashi , Masaki Okuda
IPC分类号： H03K5/151 , H03K19/00 , H03K19/003 , H03K19/21
CPC分类号： H03K5/1515 , H03K5/26 , H03K19/00323 , H03K19/21 , H03L7/0812 , H03L7/089
摘要： A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.
摘要翻译：逻辑电路接收第一和第二输入信号，其中第一逻辑电平的周期部分地重叠，并输出其中第一逻辑电平的周期不重叠的第一和第二输出信号。逻辑电路包括第一单元，当从第二逻辑电平到第一逻辑电平的第一输入信号的改变被检测到时，将第一输出信号的相位从第二逻辑电平改变到第一逻辑电平。当检测到第一输入信号的变化时，第二输入信号被检测为处于第一逻辑电平时，第二单元将第二输出信号的相位从第一逻辑电平改变为第二逻辑电平。

2. 发明授权

US07330062B2 Input/output logical circuit 有权
标题翻译：输入/输出逻辑电路
公开(公告)号：US07330062B2
公开(公告)日：2008-02-12
申请号：US11643888
申请日：2006-12-22
申请人： Hiroyuki Kobayashi , Masaki Okuda
发明人： Hiroyuki Kobayashi , Masaki Okuda
IPC分类号： H03H11/16
CPC分类号： H03K5/1515 , H03K5/26 , H03K19/00323 , H03K19/21 , H03L7/0812 , H03L7/089
摘要： A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.
摘要翻译：逻辑电路接收第一和第二输入信号，其中第一逻辑电平的周期部分地重叠，并输出其中第一逻辑电平的周期不重叠的第一和第二输出信号。逻辑电路包括第一单元，当从第二逻辑电平到第一逻辑电平的第一输入信号的改变被检测到时，将第一输出信号的相位从第二逻辑电平改变到第一逻辑电平。当检测到第一输入信号的变化时，第二输入信号被检测为处于第一逻辑电平时，第二单元将第二输出信号的相位从第一逻辑电平改变为第二逻辑电平。

3. 发明申请

US20070103218A1 Logical circuit 有权
公开(公告)号：US20070103218A1
公开(公告)日：2007-05-10
申请号：US11643888
申请日：2006-12-22
申请人： Hiroyuki Kobayashi , Masaki Okuda
发明人： Hiroyuki Kobayashi , Masaki Okuda
IPC分类号： H03K5/13
CPC分类号： H03K5/1515 , H03K5/26 , H03K19/00323 , H03K19/21 , H03L7/0812 , H03L7/089
摘要： A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.

4. 发明授权

US06728157B2 Semiconductor memory 有权
公开(公告)号：US06728157B2
公开(公告)日：2004-04-27
申请号：US10335948
申请日：2003-01-03
申请人： Yoshimasa Yagishita , Toshiya Uchida , Yoshihide Bando , Hiroyuki Kobayashi , Shusaku Yamaguchi , Masaki Okuda
发明人： Yoshimasa Yagishita , Toshiya Uchida , Yoshihide Bando , Hiroyuki Kobayashi , Shusaku Yamaguchi , Masaki Okuda
IPC分类号： G11C700
CPC分类号： G11C11/4087 , G11C11/406
摘要： A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.

5. 发明授权

US07190204B2 Logical circuit 有权
标题翻译：逻辑电路
公开(公告)号：US07190204B2
公开(公告)日：2007-03-13
申请号：US11042335
申请日：2005-01-26
申请人： Hiroyuki Kobayashi , Masaki Okuda
发明人： Hiroyuki Kobayashi , Masaki Okuda
IPC分类号： H03H11/16
CPC分类号： H03K5/1515 , H03K5/26 , H03K19/00323 , H03K19/21 , H03L7/0812 , H03L7/089
摘要： A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.
摘要翻译：逻辑电路接收第一和第二输入信号，其中第一逻辑电平的周期部分地重叠，并输出其中第一逻辑电平的周期不重叠的第一和第二输出信号。逻辑电路包括第一单元，当从第二逻辑电平到第一逻辑电平的第一输入信号的改变被检测到时，将第一输出信号的相位从第二逻辑电平改变到第一逻辑电平。当检测到第一输入信号的变化时，第二输入信号被检测为处于第一逻辑电平时，第二单元将第二输出信号的相位从第一逻辑电平改变为第二逻辑电平。

6. 发明授权

US06754126B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US06754126B2
公开(公告)日：2004-06-22
申请号：US10106597
申请日：2002-03-27
申请人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
发明人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C8/12 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4087 , G11C2211/4061 , G11C2211/4062
摘要： A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.
摘要翻译：形成多个第一存储块和用于再现第一存储块的数据的第二存储块。当读命令和刷新命令彼此冲突时，读控制电路根据刷新命令访问第一存储块，并通过使用第二存储块再现读数据。当写命令和刷新命令彼此冲突时，写控制电路根据命令接收的顺序操作存储块。因此，可以在不被用户识别的情况下进行刷新操作。即，可以提供用户友好的半导体存储器。

7. 发明授权

US06667913B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06667913B2
公开(公告)日：2003-12-23
申请号：US10285425
申请日：2002-11-01
申请人： Masaki Okuda , Hiroyuki Kobayashi
发明人： Masaki Okuda , Hiroyuki Kobayashi
IPC分类号： G11C1604
CPC分类号： G11C29/028 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C29/02 , G11C29/50 , G11C29/56012
摘要： A phase adjustment circuit delays an external clock signal to generate an adjusted clock signal. A phase comparator compares phases of the external clock signal and the adjusted clock signal, and outputs a phase adjustment signal for adjusting a delay time of the phase adjustment circuit. A data output circuit outputs read data to a data terminal in synchronization with the adjusted clock signal. A data input circuit receives write data supplied to the data terminal, in synchronization with the adjusted clock signal. When performing input of the write data and output of the read data successively, switching control between the input operation of the write data and the output operation of the read data only has to be completed within one clock cycle. The clock cycle can thus be reduced to the time required for the switching control. Consequently, maximum frequency of the external clock signal can be increased.
摘要翻译：相位调整电路延迟外部时钟信号以产生经调整的时钟信号。相位比较器比较外部时钟信号和调整后的时钟信号的相位，并输出用于调整相位调整电路的延迟时间的相位调整信号。数据输出电路与被调整的时钟信号同步地将数据输出到数据终端。数据输入电路与调整后的时钟信号同步地接收提供给数据终端的写入数据。当连续执行写入数据的输入和读取数据的输出时，必须在一个时钟周期内完成写入数据的输入操作和读取数据的输出操作之间的切换控制。因此，时钟周期可以减少到开关控制所需的时间。因此，可以增加外部时钟信号的最大频率。

8. 发明申请

US20100205306A1 GRID COMPUTING SYSTEM, MANAGEMENT APPARATUS, AND METHOD FOR MANAGING A PLURALITY OF NODES 审中-公开
标题翻译：网格计算系统，管理装置和管理多重节点的方法
公开(公告)号：US20100205306A1
公开(公告)日：2010-08-12
申请号：US12702857
申请日：2010-02-09
申请人： Hiroshi Kayanuma , Kouitirou Takahasi , Masaki Okuda
发明人： Hiroshi Kayanuma , Kouitirou Takahasi , Masaki Okuda
IPC分类号： G06F15/16 , G06F9/46 , G06F15/173
CPC分类号： G06F9/505 , G06F9/5094 , G06F2209/5019 , Y02D10/22
摘要： A grid computing system includes a plurality of nodes for processing a plurality of jobs, and a management apparatus for managing the plurality of the nodes. Each of the nodes is switchable between a standby and an active status, respectively. And the management apparatus including, a job request unit for allotting a plurality of requests of jobs to any of the nodes in an active state, a prediction unit for predicting the number of the nodes in the active state optimal for predicted amount of jobs requested from the exterior at a future time when a predetermined time period lapses from the present time, and a controller for controlling switching of the nodes between the standby and active so as to control the predicted number of the nodes to start switching before the future time.
摘要翻译：网格计算系统包括用于处理多个作业的多个节点，以及用于管理多个节点的管理装置。每个节点分别在待机状态和活动状态之间切换。并且，所述管理装置包括：作业请求单元，用于将多个作业请求分配给处于活动状态的任何节点;预测单元，用于预测所述活动状态中的节点数目，在从当前时间经过预定时间段的未来时间的外部，以及控制器，用于控制备用和活动之间的节点的切换，以便控制节点的预测数量在未来时间之前开始切换。

9. 发明申请

US20080246540A1 Semiconductor integrated circuit for voltage detection 失效
标题翻译：用于电压检测的半导体集成电路
公开(公告)号：US20080246540A1
公开(公告)日：2008-10-09
申请号：US11878748
申请日：2007-07-26
申请人： Masaki Okuda
发明人： Masaki Okuda
IPC分类号： H01L25/00
CPC分类号： H01L27/0682
摘要： A semiconductor integrated circuit includes a semiconductor substrate, one or more wells formed in the semiconductor substrate, one or more diffusion layers formed in the one or more wells, a plurality of interconnects formed in an interconnect layer, the one or more diffusion layers and the plurality of interconnects being connected in series to provide a coupling between a first potential and a second potential, and a comparison circuit coupled to one of the interconnects set at a third potential between the first potential and the second potential, and configured to compare the third potential with a reference potential, wherein a first interconnect of the plurality of interconnects that is set to the first potential is connected to at least a first well of the one or more wells and connected to a first diffusion layer of the one or more diffusion layers that is formed in the first well.
摘要翻译：半导体集成电路包括半导体衬底，形成在半导体衬底中的一个或多个阱，形成在一个或多个阱中的一个或多个扩散层，形成在互连层中的多个互连，一个或多个扩散层和多个互连串联连接以提供第一电位和第二电位之间的耦合，以及比较电路，其耦合到设置在第一电位和第二电位之间的第三电位的互连中的一个，并且被配置为将第三电位具有参考电位的电位，其中被设置为第一电位的多个互连的第一互连连接到所述一个或多个阱的至少第一阱并连接到所述一个或多个扩散层的第一扩散层这是在第一口井中形成的。

10. 发明申请

US20100112353A1 ELECTROCONDUCTIVE FINE PARTICLES, ANISOTROPIC ELECTROCONDUCTIVE MATERIAL, AND ELECTROCONDUCTIVE CONNECTION STRUCTURE 有权
标题翻译：电磁精细颗粒，非均质电极材料和电磁连接结构
公开(公告)号：US20100112353A1
公开(公告)日：2010-05-06
申请号：US12450704
申请日：2008-03-31
申请人： Ren-de Sun , Kiyoto Matsushita , Taku Sasaki , Shinya Uenoyama , Masaki Okuda , Nobuyuki Okinaga
发明人： Ren-de Sun , Kiyoto Matsushita , Taku Sasaki , Shinya Uenoyama , Masaki Okuda , Nobuyuki Okinaga
IPC分类号： B32B15/02
CPC分类号： H05K3/323 , B23K35/262 , B23K2101/36 , C23C18/1635 , C23C18/1653 , C23C18/1692 , C23C18/30 , C23C18/34 , C23C18/54 , H01L24/29 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/29311 , H01L2224/2939 , H01L2224/29411 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01327 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/04941 , H01L2924/0665 , H01L2924/07811 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01R13/03 , H05K2201/0221 , H05K2203/0425 , Y10T428/2982 , Y10T428/2998 , H01L2924/00 , H01L2924/01028 , H01L2924/3512 , H01L2924/00012 , H01L2924/00014
摘要： It is an object of the present invention to provide: a conductive fine particle, which is used for conductive connection between fine electrodes and tends not to give rise to a crack in the solder layer or disconnection caused by breakage in the connection interface between an electrode and the conductive fine particle even with a drop impact and the like, and tends not to have fatigue even after repetitive heating and cooling; an anisotropic conductive material obtained by using the conductive fine particle; and a conductive connection structure.The present invention relates to a conductive fine particle, which comprises a solder layer containing tin and being formed on a surface of a resin fine particle, with nickel adhered to a surface of the solder layer, and contains 0.0001 to 5.0% by weight of the nickel with respect to a total of a metal contained in the solder layer and the nickel adhered to the surface of the solder layer.
摘要翻译：本发明的目的是提供：导电性微粒，用于在细电极之间进行导电连接，并且不会引起焊料层中的裂纹或由电极之间的连接界面中的断裂引起的断开导电性细颗粒即使具有液滴冲击等，并且即使在重复加热和冷却之后也不会有疲劳; 通过使用导电性微粒获得的各向异性导电材料; 和导电连接结构。本发明涉及一种导电性细颗粒，其包含含锡的焊料层，并且形成在树脂细颗粒的表面上，镍附着在焊料层的表面上，并且含有0.0001至5.0重量％的镍相对于焊料层中包含的总量和附着到焊料层表面的镍。

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