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1. 发明授权

US08609246B2 Electroconductive fine particles, anisotropic electroconductive material, and electroconductive connection structure 有权
标题翻译：导电细颗粒，各向异性导电材料和导电连接结构
公开(公告)号：US08609246B2
公开(公告)日：2013-12-17
申请号：US12450704
申请日：2008-03-31
申请人： Ren-de Sun , Kiyoto Matsushita , Taku Sasaki , Shinya Uenoyama , Masaki Okuda , Nobuyuki Okinaga
发明人： Ren-de Sun , Kiyoto Matsushita , Taku Sasaki , Shinya Uenoyama , Masaki Okuda , Nobuyuki Okinaga
IPC分类号： B32B15/02
CPC分类号： H05K3/323 , B23K35/262 , B23K2101/36 , C23C18/1635 , C23C18/1653 , C23C18/1692 , C23C18/30 , C23C18/34 , C23C18/54 , H01L24/29 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/29311 , H01L2224/2939 , H01L2224/29411 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01327 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/04941 , H01L2924/0665 , H01L2924/07811 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01R13/03 , H05K2201/0221 , H05K2203/0425 , Y10T428/2982 , Y10T428/2998 , H01L2924/00 , H01L2924/01028 , H01L2924/3512 , H01L2924/00012 , H01L2924/00014
摘要： A conductive fine particle, which is used for conductive connection between fine electrodes and tends not to give rise to a crack in the solder layer or disconnection caused by breakage in the connection interface between an electrode and the conductive fine particle even with a drop impact and the like, and tends not to have fatigue even after repetitive heating and cooling; an anisotropic conductive material obtained by using the conductive fine particle; and a conductive connection structure.
摘要翻译：导电性细颗粒，用于细电极之间的导电连接，并且即使具有落下冲击，也不会引起焊料层中的裂纹或由于电极和导电性细颗粒之间的连接界面的断裂而导致的断开，即使在重复加热和冷却之后也不会有疲劳; 通过使用导电性微粒获得的各向异性导电材料; 和导电连接结构。

2. 发明申请

US20100112353A1 ELECTROCONDUCTIVE FINE PARTICLES, ANISOTROPIC ELECTROCONDUCTIVE MATERIAL, AND ELECTROCONDUCTIVE CONNECTION STRUCTURE 有权
标题翻译：电磁精细颗粒，非均质电极材料和电磁连接结构
公开(公告)号：US20100112353A1
公开(公告)日：2010-05-06
申请号：US12450704
申请日：2008-03-31
申请人： Ren-de Sun , Kiyoto Matsushita , Taku Sasaki , Shinya Uenoyama , Masaki Okuda , Nobuyuki Okinaga
发明人： Ren-de Sun , Kiyoto Matsushita , Taku Sasaki , Shinya Uenoyama , Masaki Okuda , Nobuyuki Okinaga
IPC分类号： B32B15/02
CPC分类号： H05K3/323 , B23K35/262 , B23K2101/36 , C23C18/1635 , C23C18/1653 , C23C18/1692 , C23C18/30 , C23C18/34 , C23C18/54 , H01L24/29 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/29311 , H01L2224/2939 , H01L2224/29411 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01327 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/04941 , H01L2924/0665 , H01L2924/07811 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01R13/03 , H05K2201/0221 , H05K2203/0425 , Y10T428/2982 , Y10T428/2998 , H01L2924/00 , H01L2924/01028 , H01L2924/3512 , H01L2924/00012 , H01L2924/00014
摘要： It is an object of the present invention to provide: a conductive fine particle, which is used for conductive connection between fine electrodes and tends not to give rise to a crack in the solder layer or disconnection caused by breakage in the connection interface between an electrode and the conductive fine particle even with a drop impact and the like, and tends not to have fatigue even after repetitive heating and cooling; an anisotropic conductive material obtained by using the conductive fine particle; and a conductive connection structure.The present invention relates to a conductive fine particle, which comprises a solder layer containing tin and being formed on a surface of a resin fine particle, with nickel adhered to a surface of the solder layer, and contains 0.0001 to 5.0% by weight of the nickel with respect to a total of a metal contained in the solder layer and the nickel adhered to the surface of the solder layer.
摘要翻译：本发明的目的是提供：导电性微粒，用于在细电极之间进行导电连接，并且不会引起焊料层中的裂纹或由电极之间的连接界面中的断裂引起的断开导电性细颗粒即使具有液滴冲击等，并且即使在重复加热和冷却之后也不会有疲劳; 通过使用导电性微粒获得的各向异性导电材料; 和导电连接结构。本发明涉及一种导电性细颗粒，其包含含锡的焊料层，并且形成在树脂细颗粒的表面上，镍附着在焊料层的表面上，并且含有0.0001至5.0重量％的镍相对于焊料层中包含的总量和附着到焊料层表面的镍。

3. 发明申请

US20100205306A1 GRID COMPUTING SYSTEM, MANAGEMENT APPARATUS, AND METHOD FOR MANAGING A PLURALITY OF NODES 审中-公开
标题翻译：网格计算系统，管理装置和管理多重节点的方法
公开(公告)号：US20100205306A1
公开(公告)日：2010-08-12
申请号：US12702857
申请日：2010-02-09
申请人： Hiroshi Kayanuma , Kouitirou Takahasi , Masaki Okuda
发明人： Hiroshi Kayanuma , Kouitirou Takahasi , Masaki Okuda
IPC分类号： G06F15/16 , G06F9/46 , G06F15/173
CPC分类号： G06F9/505 , G06F9/5094 , G06F2209/5019 , Y02D10/22
摘要： A grid computing system includes a plurality of nodes for processing a plurality of jobs, and a management apparatus for managing the plurality of the nodes. Each of the nodes is switchable between a standby and an active status, respectively. And the management apparatus including, a job request unit for allotting a plurality of requests of jobs to any of the nodes in an active state, a prediction unit for predicting the number of the nodes in the active state optimal for predicted amount of jobs requested from the exterior at a future time when a predetermined time period lapses from the present time, and a controller for controlling switching of the nodes between the standby and active so as to control the predicted number of the nodes to start switching before the future time.
摘要翻译：网格计算系统包括用于处理多个作业的多个节点，以及用于管理多个节点的管理装置。每个节点分别在待机状态和活动状态之间切换。并且，所述管理装置包括：作业请求单元，用于将多个作业请求分配给处于活动状态的任何节点;预测单元，用于预测所述活动状态中的节点数目，在从当前时间经过预定时间段的未来时间的外部，以及控制器，用于控制备用和活动之间的节点的切换，以便控制节点的预测数量在未来时间之前开始切换。

4. 发明申请

US20080246540A1 Semiconductor integrated circuit for voltage detection 失效
标题翻译：用于电压检测的半导体集成电路
公开(公告)号：US20080246540A1
公开(公告)日：2008-10-09
申请号：US11878748
申请日：2007-07-26
申请人： Masaki Okuda
发明人： Masaki Okuda
IPC分类号： H01L25/00
CPC分类号： H01L27/0682
摘要： A semiconductor integrated circuit includes a semiconductor substrate, one or more wells formed in the semiconductor substrate, one or more diffusion layers formed in the one or more wells, a plurality of interconnects formed in an interconnect layer, the one or more diffusion layers and the plurality of interconnects being connected in series to provide a coupling between a first potential and a second potential, and a comparison circuit coupled to one of the interconnects set at a third potential between the first potential and the second potential, and configured to compare the third potential with a reference potential, wherein a first interconnect of the plurality of interconnects that is set to the first potential is connected to at least a first well of the one or more wells and connected to a first diffusion layer of the one or more diffusion layers that is formed in the first well.
摘要翻译：半导体集成电路包括半导体衬底，形成在半导体衬底中的一个或多个阱，形成在一个或多个阱中的一个或多个扩散层，形成在互连层中的多个互连，一个或多个扩散层和多个互连串联连接以提供第一电位和第二电位之间的耦合，以及比较电路，其耦合到设置在第一电位和第二电位之间的第三电位的互连中的一个，并且被配置为将第三电位具有参考电位的电位，其中被设置为第一电位的多个互连的第一互连连接到所述一个或多个阱的至少第一阱并连接到所述一个或多个扩散层的第一扩散层这是在第一口井中形成的。

5. 发明授权

US07675773B2 Semiconductor memory, test method of semiconductor memory and system 失效
标题翻译：半导体存储器，半导体存储器和系统的测试方法
公开(公告)号：US07675773B2
公开(公告)日：2010-03-09
申请号：US12130480
申请日：2008-05-30
申请人： Kaoru Mori , Toshikazu Nakamura , Jun Ohno , Masaki Okuda
发明人： Kaoru Mori , Toshikazu Nakamura , Jun Ohno , Masaki Okuda
IPC分类号： G11C11/34
CPC分类号： G11C8/18 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C29/1201 , G11C29/18 , G11C29/48 , G11C2029/1802
摘要： An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced.
摘要翻译：地址开关电路接收提供给第一地址端子组的行地址信号和提供给第二地址端子组的列地址信号。此外，地址开关电路接收提供给第二地址端子组的行地址信号，然后接收提供给第二地址端子组的列地址信号，并将接收到的行地址信号和接收的列地址信号提供给行解码器，列解码器在第二操作模式期间。可以通过在第二操作模式中执行半导体存储器的操作测试来增加一次测试的半导体存储器的数量。此外，可以使用用于其他半导体存储器的测试资产来测试半导体存储器。因此，可以提高测试效率，并且可以降低测试成本。

6. 发明授权

US07427885B2 Semiconductor device having a power supply capacitor 有权
标题翻译：具有电源电容器的半导体装置
公开(公告)号：US07427885B2
公开(公告)日：2008-09-23
申请号：US11020169
申请日：2004-12-27
申请人： Masaki Okuda
发明人： Masaki Okuda
IPC分类号： G06F1/04
CPC分类号： G06F1/26 , H01L2924/0002 , H01L2924/00
摘要： In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals; a first MOS capacitor in which a gate of a p-channel MOS field effect transistor is connected to the low reference potential terminal, and a source and a drain are connected to the high reference potential terminal; and a first signal wiring connected to the gate via a parasitic capacitor and a signal in the low reference potential is supplied at the time of starting the power supply.
摘要翻译：为了防止信号线的信号由于电源电容器而受到不良影响，提供了包括构成电源电压端子的高参考电位端子和低基准电位端子的半导体; 第一MOS电容器，其中p沟道MOS场效应晶体管的栅极连接到低参考电势端子，源极和漏极连接到高参考电位端子; 并且在开始供电时提供经由寄生电容器连接到栅极的第一信号线和低基准电位的信号。

7. 发明申请

US20050168245A1 Logical circuit 有权
标题翻译：逻辑电路
公开(公告)号：US20050168245A1
公开(公告)日：2005-08-04
申请号：US11042335
申请日：2005-01-26
申请人： Hiroyuki Kobayashi , Masaki Okuda
发明人： Hiroyuki Kobayashi , Masaki Okuda
IPC分类号： H03K5/151 , H03K19/00 , H03K19/003 , H03K19/21
CPC分类号： H03K5/1515 , H03K5/26 , H03K19/00323 , H03K19/21 , H03L7/0812 , H03L7/089
摘要： A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.
摘要翻译：逻辑电路接收第一和第二输入信号，其中第一逻辑电平的周期部分地重叠，并输出其中第一逻辑电平的周期不重叠的第一和第二输出信号。逻辑电路包括第一单元，当从第二逻辑电平到第一逻辑电平的第一输入信号的改变被检测到时，将第一输出信号的相位从第二逻辑电平改变到第一逻辑电平。当检测到第一输入信号的变化时，第二输入信号被检测为处于第一逻辑电平时，第二单元将第二输出信号的相位从第一逻辑电平改变为第二逻辑电平。

8. 发明授权

US06922750B2 Semiconductor memory device capable of simultaneously reading data and refreshing data 失效
标题翻译：能够同时读取数据和刷新数据的半导体存储器件
公开(公告)号：US06922750B2
公开(公告)日：2005-07-26
申请号：US10046754
申请日：2002-01-17
申请人： Masaki Okuda
发明人： Masaki Okuda
IPC分类号： G01R31/28 , G06F12/16 , G11C7/10 , G11C11/401 , G11C11/406 , G11C11/4096 , G11C29/42 , G06F12/00
CPC分类号： G11C7/1006 , G11C11/406 , G11C11/4096
摘要： A semiconductor memory device is capable of simultaneously reading data and refreshing data and checking whether a data restoring function is operating normally. A data inputting circuit receives data inputted from an external circuit. A parity generating circuit generates parity data from the data input from the data inputting circuit. A memory stores the data input from the data inputting circuit and the parity data generated by the parity generating circuit. A refreshing circuit refreshes the memory. A reading circuit reads the data from the memory. A restoring circuit restores data to be refreshed by the refreshing circuit from other data read normally and corresponding parity data, while the reading circuit is reading data. A data outputting circuit outputs the data read by the reading circuit and the data restored by the restoring circuit. A parity outputting circuit directly reads and outputs the parity data stored in the memory.
摘要翻译：半导体存储器件能够同时读取数据和刷新数据，并检查数据恢复功能是否正常工作。数据输入电路接收从外部电路输入的数据。奇偶生成电路从数据输入电路输入的数据生成奇偶校验数据。存储器存储从数据输入电路输入的数据和由奇偶产生电路产生的奇偶校验数据。刷新电路刷新内存。读取电路从存储器读取数据。当读取电路正在读取数据时，恢复电路恢复由正常读取的其他数据和对应的奇偶校验数据由刷新电路刷新的数据。数据输出电路输出由读取电路读取的数据和由恢复电路恢复的数据。奇偶校验输出电路直接读取并输出存储在存储器中的奇偶校验数据。

9. 发明授权

US06199025B1 Semiconductor device having selectable device type and methods of testing device operation 失效
标题翻译：具有可选设备类型的半导体器件和测试器件操作的方法
公开(公告)号：US06199025B1
公开(公告)日：2001-03-06
申请号：US09010547
申请日：1998-01-22
申请人： Atsushi Fujii , Masaki Okuda
发明人： Atsushi Fujii , Masaki Okuda
IPC分类号： G11C700
CPC分类号： G11C17/16 , G01R31/31701 , G11C29/46 , G11C29/48
摘要： A semiconductor device includes a device-type switching circuit which determines selection signals A based on fuse-cut conditions in a first mode, and determines selection signals based on control signals supplied thereto in a second mode, and an internal circuit having an operation thereof selected by selection signals from device-type switching circuit.
摘要翻译：半导体器件包括：器件型切换电路，其基于第一模式中的熔丝切断条件来确定选择信号A，并且基于在第二模式中提供给其的控制信号来确定选择信号;以及内部电路，其选择其操作通过来自器件型开关电路的选择信号。

10. 发明授权

US07557645B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07557645B2
公开(公告)日：2009-07-07
申请号：US11802455
申请日：2007-05-23
申请人： Masaki Okuda
发明人： Masaki Okuda
IPC分类号： H01L25/00
CPC分类号： G06F1/26 , H01L2924/0002 , H01L2924/00
摘要： In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals; a first MOS capacitor in which a gate of a p-channel MOS field effect transistor is connected to the low reference potential terminal, and a source and a drain are connected to the high reference potential terminal; and a first signal wiring connected to the gate via a parasitic capacitor and a signal in the low reference potential is supplied at the time of starting the power supply.
摘要翻译：为了防止信号线的信号由于电源电容器而受到不良影响，提供了包括构成电源电压端子的高参考电位端子和低基准电位端子的半导体; 第一MOS电容器，其中p沟道MOS场效应晶体管的栅极连接到低参考电势端子，源极和漏极连接到高参考电位端子; 并且在开始供电时提供经由寄生电容器连接到栅极的第一信号线和低基准电位的信号。

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