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1. 发明授权

US3983619A Large scale integrated circuit array of unit cells and method of manufacturing same 失效
标题翻译：单位电池的大规模集成电路阵列及其制造方法
公开(公告)号：US3983619A
公开(公告)日：1976-10-05
申请号：US394631
申请日：1973-09-06
申请人： Masaharu Kubo , Minoru Nagata , Keikichi Moriwaki
发明人： Masaharu Kubo , Minoru Nagata , Keikichi Moriwaki
IPC分类号： H01L27/118 , B01J17/00
CPC分类号： H01L27/11803 , Y10S257/909
摘要： A semiconductor LSI array comprising a plurality of unit cells arranged in rows, each of which cells has operation terminals, input terminals and output terminals positioned in a standardized relation. A set of runways are provided on the unit cells for each row so that the runways may be connected to corresponding operation terminals and that input terminals may be opposed to output terminals with respect to the runways.
摘要翻译：一种半导体LSI阵列，包括排列成行的多个单位单元，每个单元具有操作终端，输入端子和以标准化关系定位的输出端子。在每一行的单位单元上提供一组跑道，使得跑道可以连接到相应的操作终端，并且输入终端可以相对于跑道相对于输出终端。

2. 发明授权

US4011581A MOSFET antiparasitic layer 失效
标题翻译： MOSFET反寄生层
公开(公告)号：US4011581A
公开(公告)日：1977-03-08
申请号：US68973
申请日：1970-09-02
申请人： Masaharu Kubo , Minoru Nagata , Yasunobu Kosa
发明人： Masaharu Kubo , Minoru Nagata , Yasunobu Kosa
IPC分类号： H01L29/78 , H01L21/76 , H01L23/29 , H01L27/02 , H01L27/092 , H01L29/00 , H01L29/06 , H01L27/04
CPC分类号： H01L29/0638 , H01L23/291 , H01L27/0251 , H01L27/0927 , H01L29/00 , H01L2924/0002 , H01L2924/13091
摘要： A semiconductor device which is provided, for the purpose of eliminating parasitic MOSFETs formed between at least two circuit elements (such as MOSFET, TRANSISTOR, RESISTOR, and the like) on a semiconductor substrate, with a high impurity concentration layer of the same conduction type as the substrate in a manner such that the layer is not only in the semiconductor substrate between said circuit elements but is also partially overlapped by the circuit element regions.
摘要翻译：为了消除形成在半导体衬底上的至少两个电路元件（例如MOSFET，晶体管，电阻等）之间的寄生MOSFET，提供了具有相同导电类型的高杂质浓度层的半导体器件作为基板，使得该层不仅在所述电路元件之间的半导体基板中，而且也部分地与电路元件区域重叠。

3. 发明授权

US4015281A MIS-FETs isolated on common substrate 失效
标题翻译：在公共基板上隔离的MIS-FET
公开(公告)号：US4015281A
公开(公告)日：1977-03-29
申请号：US121375
申请日：1971-03-05
申请人： Minoru Nagata , Toshiaki Masuhara , Masaharu Kubo , Norikazu Hashimoto
发明人： Minoru Nagata , Toshiaki Masuhara , Masaharu Kubo , Norikazu Hashimoto
IPC分类号： H01L21/765 , H01L27/088 , H01L29/51 , H01L27/02
CPC分类号： H01L29/511 , H01L21/765 , H01L27/0883
摘要： An enhancement-type and a depletion-type metal-insulator-semiconductor field effect transistor are formed on a common substrate of silicon and are electrically isolated from each other by a plurality of layers including, for example, a first layer of SiO.sub.2, a second layer of Al.sub.2 O.sub.3 capable of inducing holes in the surface portion of the substrate, and a third layer of SiO.sub.2, and the relation between the thicknesses of these layers is suitably selected for attaining the satisfactory isolation between these transistors.
摘要翻译：增强型和耗尽型金属 - 绝缘体 - 半导体场效应晶体管形成在公共的硅衬底上，并且通过多个层彼此电隔离，所述多个层包括例如第一SiO 2层，第二层能够在衬底的表面部分中引入空穴的Al 2 O 3层和SiO 3层，并且适当地选择这些层的厚度之间的关系以获得这些晶体管之间的令人满意的隔离。

4. 发明申请

US20100176869A1 TEMPERATURE COMPENSATION CIRCUIT 有权
标题翻译：温度补偿电路
公开(公告)号：US20100176869A1
公开(公告)日：2010-07-15
申请号：US12686613
申请日：2010-01-13
申请人： Koji Horie , Minoru Nagata
发明人： Koji Horie , Minoru Nagata
IPC分类号： H01L37/00
CPC分类号： H03F1/302 , H03F3/195 , H03F3/245 , H03F2200/447 , H03F2200/451
摘要： A temperature compensation circuit according to an embodiment of the present invention includes a bias circuit configured to output a bias current having a current value increasing in proportion to an absolute temperature in a low-temperature region in which a temperature is lower than a predetermined temperature, and having a greater current value than the current value proportional to the absolute temperature in a high-temperature region in which the temperature is equal to or greater than the predetermined temperature, and a transistor having a control terminal supplied with the bias current. The bias circuit includes a first current generating circuit configured to generate a first current increasing in proportion to the absolute temperature, a second current generating circuit configured to generate a second current that does not flow in the low-temperature region and flows in the high-temperature region, and a control circuit configured to control the second current and having a connection terminal capable of being connected with an external resistor for adjusting a magnitude of the second current, and is configured to generate a third current by adding the first current to the second current, and output the bias current depending on or equal to the third current.
摘要翻译：根据本发明实施例的温度补偿电路包括：偏置电路，被配置为输出与温度低于预定温度的低温区域中的绝对温度成比例地增加的电流值的偏置电流，并且具有比在温度等于或大于预定温度的高温区域中与绝对温度成比例的电流值的电流值更大的电流值，以及具有提供偏置电流的控制端子的晶体管。偏置电路包括：第一电流产生电路，被配置为产生与绝对温度成比例的第一电流;第二电流产生电路，被配置为产生不在低温区域中流动并在高温区域中流动的第二电流; 温度区域和控制电路，被配置为控制第二电流并具有能够与外部电阻器连接的连接端子，用于调整第二电流的大小，并且被配置为通过将第一电流加到第一电流中来产生第三电流并且根据或等于第三电流输出偏置电流。

5. 发明授权

US5842123A Radio paging system with voice transfer function and radio pager 失效
公开(公告)号：US5842123A
公开(公告)日：1998-11-24
申请号：US425736
申请日：1995-04-20
申请人： Nobuo Hamamoto , Tadashi Onishi , Tatsundo Suzuki , Minoru Nagata , Kenichi Mizuishi , Yosuke Tyojamori
发明人： Nobuo Hamamoto , Tadashi Onishi , Tatsundo Suzuki , Minoru Nagata , Kenichi Mizuishi , Yosuke Tyojamori
IPC分类号： G08B3/10 , G08B5/22 , H04M3/533 , H04M11/02 , H04W88/18 , H04M11/10
CPC分类号： H04W88/187 , G08B3/1025 , G08B5/229 , H04M11/022 , H04M3/533 , H04M2203/609
摘要： A radio paging system with voice transfer function for transmitting a voice message input from an ordinary push-button telephone set to a small-sized receive-only unsophisticated radio pager. A paging station is provided to transmit by radio the message from a telephone network to the radio pager as follows: voice information constituting the message is first converted from analog to digital format, compressed, stored in memory, and scrambled by a privacy function part for transmission. The radio pager in turn demodulates the received information, stores it in memory, retrieves a necessary message therefrom as designated, descrambles the designated message from scrambled state, expands the message from compressed state, and outputs the message as an audible output. In this manner, the user carrying the radio pager is able to get the message from the caller without the risk of being tapped by a third party.

6. 发明授权

US4860086A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4860086A
公开(公告)日：1989-08-22
申请号：US26254
申请日：1987-03-16
申请人： Tohru Nakamura , Masahiko Ogirima , Kazuo Nakazato , Takao Miyazaki , Naoki Yamamoto , Minoru Nagata , Shojiro Sugaki, deceased
发明人： Tohru Nakamura , Masahiko Ogirima , Kazuo Nakazato , Takao Miyazaki , Naoki Yamamoto , Minoru Nagata , Shojiro Sugaki, deceased
IPC分类号： H01L23/485 , H01L23/532
CPC分类号： H01L23/53271 , H01L23/485 , H01L2924/0002
摘要： A semiconductor device is constructed so that an insulation film is provided in regions other than a protruding portion of a substrate. A polycrystalline silicon layer and a metal silicide layer are formed over said insulation film to provide a multi-layer structure, and a take-out portion for at least one of the emitter, base, and collector members of a bipolar transistor provided in the mesa region is constituted by a film of this multi-layer structure. By virtue of the use of metal silicide together with the polycrystalline silicon, a very low resistance is achieved which enhances the device's operating speed. Further, the metal silicide is separated from the protruding portion of the substrate by a portion of the polycrystalline silicon to provide a smooth interface with the substrate. This smooth interface significantly reduces crystal defects in the single crystal substrate.
摘要翻译：构造半导体器件，使得绝缘膜设置在除了衬底的突出部分之外的区域中。在所述绝缘膜上形成多晶硅层和金属硅化物层以提供多层结构，以及设置在台面中的双极晶体管的发射极，基极和集电极构件中的至少一个的取出部分区域由该多层结构的膜构成。由于金属硅化物与多晶硅一起使用，所以实现了非常低的电阻，这增强了器件的工作速度。此外，金属硅化物通过多晶硅的一部分与衬底的突出部分分离，以提供与衬底的平滑界面。这种平滑的界面显着地减少了单晶衬底中的晶体缺陷。

7. 发明授权

US4857769A Threshold voltage fluctuation compensation circuit for FETS 失效
标题翻译： FETS的阈值电压波动补偿电路
公开(公告)号：US4857769A
公开(公告)日：1989-08-15
申请号：US143385
申请日：1988-01-13
申请人： Nobuo Kotera , Kiichi Yamashita , Taizo Kinoshita , Hirotoshi Tanaka , Satoshi Tanaka , Minoru Nagata
发明人： Nobuo Kotera , Kiichi Yamashita , Taizo Kinoshita , Hirotoshi Tanaka , Satoshi Tanaka , Minoru Nagata
IPC分类号： H03K19/003
CPC分类号： H03K19/00384
摘要： This invention relates to a threshold voltage detection circuit for detecting the threshold voltage of field effect transistors (FETs) and to a semiconductor circuit capable of a stable operation irrespective of the fluctuation of the threshold voltage by utilizing this threshold voltage detection circuit. The source-drain path of first FET is connected in series with that of second FET having substantially the same threshold voltage as that of the first FET and the conductances of these first and second FETs are set to a predetermined ratio to generate a voltage drop associated with the threshold voltage in the first FET. This voltage drop can be used for detecting the threshold voltage and for level-shifting. The output of the series connection of the first and second FETs is applied to the gate of a constant current FET having the same threshold voltage as that of the first and second FETs and the drain current of the constant current FET can thus be set irrespective of the fluctuation of the threshold voltage.
摘要翻译：本发明涉及一种阈值电压检测电路，用于通过利用该阈值电压检测电路来检测场效应晶体管（FET）的阈值电压和能够稳定工作的半导体电路，而与阈值电压的波动无关。第一FET的源极 - 漏极路径与具有与第一FET基本相同的阈值电压的第二FET的源极 - 漏极路径串联连接，并且将这些第一和第二FET的电导设置为预定的比率以产生相关的电压降与第一FET中的阈值电压。该电压降可用于检测阈值电压和电平转换。第一和第二FET的串联连接的输出被施加到具有与第一和第二FET相同的阈值电压的恒流FET的栅极，因此可以设定恒定电流FET的漏极电流，而不管阈值电压的波动。

8. 发明授权

US4825281A Bipolar transistor with sidewall bare contact structure 失效
标题翻译：双极晶体管与侧壁裸接触结构
公开(公告)号：US4825281A
公开(公告)日：1989-04-25
申请号：US435552
申请日：1982-10-21
申请人： Kazuo Nakazato , Tohru Nakamura , Masatoshi Matsuda , Takao Miyazaki , Tokuo Kure , Takahiro Okabe , Minoru Nagata
发明人： Kazuo Nakazato , Tohru Nakamura , Masatoshi Matsuda , Takao Miyazaki , Tokuo Kure , Takahiro Okabe , Minoru Nagata
IPC分类号： H01L21/8222 , H01L21/033 , H01L21/3205 , H01L21/331 , H01L27/06 , H01L29/423 , H01L29/70 , H01L29/72 , H01L29/73 , H01L29/732 , H01L29/735 , H01L23/48 , H01L29/04 , H01L29/34
CPC分类号： H01L29/66272 , H01L21/033 , H01L29/42304 , H01L29/72 , H01L29/732 , H01L29/735
摘要： A semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.
摘要翻译：一种半导体器件，其中晶体管的有源区形成在设置在绝缘膜中的开口中，电极由形成在绝缘膜上的多晶硅膜引出，发射极和基极的上表面和暴露表面的绝缘膜基本上均匀。

9. 发明授权

US08456227B2 Current mirror circuit 失效
标题翻译：电流镜电路
公开(公告)号：US08456227B2
公开(公告)日：2013-06-04
申请号：US13046953
申请日：2011-03-14
申请人： Kenichi Hirashiki , Norio Hagiwara , Tsutomu Nakashima , Minoru Nagata
发明人： Kenichi Hirashiki , Norio Hagiwara , Tsutomu Nakashima , Minoru Nagata
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs.
摘要翻译：在一个实施例中，电流镜电路包括第一至第四绝缘栅场效应晶体管（FET）和偏置电路。第一和第二FET的栅电极彼此连接。第三FET的源电极连接到第一FET的漏电极，第三FET的漏电极连接到第一和第二FET的栅电极以及电流输入端。第四FET的栅电极与第三FET的栅电极连接，第四FET的源电极与第二FET的漏极连接，第四FET的漏极成为电流输出端。偏置电路被配置为向第三和第四FET的栅电极提供偏置电压。

10. 发明申请

US20110234311A1 CURRENT DETECTION CIRCUIT AND INFORMATION TERMINAL 审中-公开
标题翻译：电流检测电路和信息终端
公开(公告)号：US20110234311A1
公开(公告)日：2011-09-29
申请号：US13047000
申请日：2011-03-14
申请人： Kenichi Hirashiki , Minoru Nagata
发明人： Kenichi Hirashiki , Minoru Nagata
IPC分类号： H03H11/00
CPC分类号： G01R19/0092
摘要： According to one embodiment, a current detection circuit is provided with: a NMOS transistor, whose control signal is given to a gate electrode, whose source electrode is connected to a ground line, and whose drain electrode is connected to an input/output terminal; a first PMOS transistor, in which the control signal is given to a gate electrode, and whose drain electrode is connected to the input/output terminal and the drain electrode of the NMOS transistor; and a second PMOS transistor, whose drain electrode is connected to the source electrode of the first PMOS transistor, and a first supply voltage is given to a source electrode. A detection section detects whether or not a current has changed at the input/output terminal from a change in current flowing through the second PMOS transistor.
摘要翻译：根据一个实施例，电流检测电路具有：NMOS晶体管，其控制信号被提供给栅电极，源电极连接到接地线，其漏电极连接到输入/输出端; 第一PMOS晶体管，其中控制信号被提供给栅电极，并且其漏电极连接到NMOS晶体管的输入/输出端子和漏电极; 以及第二PMOS晶体管，其漏极连接到第一PMOS晶体管的源电极，并且向源电极提供第一电源电压。检测部分检测在流过第二PMOS晶体管的电流的变化中电流是否在输入/输出端子处改变。

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