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1. 发明申请

US20090004805A1 Damage Implantation of a Cap Layer 有权
标题翻译：盖层的损伤植入
公开(公告)号：US20090004805A1
公开(公告)日：2009-01-01
申请号：US11771269
申请日：2007-06-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/336 , H01L23/58
CPC分类号： H01L29/7847 , H01L21/31155 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L29/6659
摘要： A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
摘要翻译：一种用于在半导体晶片上制造晶体管的方法包括提供包含栅极堆叠，延伸区域和源极/漏极侧壁的部分晶体管。该方法还包括执行半导体晶片的源极/漏极注入，在半导体晶片上形成覆盖层，并执行源极/漏极退火。此外，该方法包括执行盖层的损伤注入并去除半导体晶片上的覆盖层。

2. 发明申请

US20090170277A1 IMPLANT DAMAGE OF LAYER FOR EASY REMOVAL AND REDUCED SILICON RECESS 有权
标题翻译：对于易于去除和减少的硅损伤的层的损伤
公开(公告)号：US20090170277A1
公开(公告)日：2009-07-02
申请号：US12345414
申请日：2008-12-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/764 , H01L21/302
CPC分类号： H01L21/76254 , H01L21/3086 , H01L21/31111 , H01L21/32139
摘要： A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.
摘要翻译：提供一种用于半导体处理的方法，其中通过离子注入在结构上弱化一个或多个层来帮助去除一层或多层。提供具有形成在其上的一个或多个初级层的半导体衬底，并且在一个或多个初级层上形成二次层。一个或多个离子种类被注入到二次层中，其中结构上弱化了二次层，并且在二级层上形成图案化的光致抗蚀剂层。除去未被图案化光致抗蚀剂层覆盖的二次层和一个或多个初级层的各部分，并进一步除去图案化的光致抗蚀剂层。第二层的至少另一部分被去除，其中次级层的结构弱化增加了次级层的至少另一部分的去除速率。

3. 发明授权

US07772094B2 Implant damage of layer for easy removal and reduced silicon recess 有权
标题翻译：植入物损伤层易于去除和减少硅凹陷
公开(公告)号：US07772094B2
公开(公告)日：2010-08-10
申请号：US12345414
申请日：2008-12-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/322
CPC分类号： H01L21/76254 , H01L21/3086 , H01L21/31111 , H01L21/32139
摘要： A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.
摘要翻译：提供一种用于半导体处理的方法，其中通过离子注入在结构上弱化一个或多个层来帮助去除一层或多层。提供具有形成在其上的一个或多个初级层的半导体衬底，并且在一个或多个初级层上形成二次层。一个或多个离子种类被注入到二次层中，其中结构上弱化了二次层，并且在二级层上形成图案化的光致抗蚀剂层。除去未被图案化光致抗蚀剂层覆盖的二次层和一个或多个初级层的各部分，并进一步除去图案化的光致抗蚀剂层。第二层的至少另一部分被去除，其中次级层的结构弱化增加了次级层的至少另一部分的去除速率。

4. 发明授权

US08859377B2 Damage implantation of a cap layer 有权
标题翻译：损伤植入帽层
公开(公告)号：US08859377B2
公开(公告)日：2014-10-14
申请号：US11771269
申请日：2007-06-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/336 , H01L29/78 , H01L21/8238 , H01L29/66 , H01L21/3115
CPC分类号： H01L29/7847 , H01L21/31155 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L29/6659
摘要： A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
摘要翻译：一种用于在半导体晶片上制造晶体管的方法包括提供包含栅极堆叠，延伸区域和源极/漏极侧壁的部分晶体管。该方法还包括执行半导体晶片的源极/漏极注入，在半导体晶片上形成覆盖层，以及执行源/漏退火。此外，该方法包括执行盖层的损伤注入并去除半导体晶片上的覆盖层。

5. 发明申请

US20100252887A1 Damage Implantation of a Cap Layer 审中-公开
标题翻译：盖层的损伤植入
公开(公告)号：US20100252887A1
公开(公告)日：2010-10-07
申请号：US12817829
申请日：2010-06-17
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L29/78
CPC分类号： H01L29/7847 , H01L21/31155 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L29/6659
摘要： A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
摘要翻译：一种用于在半导体晶片上制造晶体管的方法包括提供包含栅极堆叠，延伸区域和源极/漏极侧壁的部分晶体管。该方法还包括执行半导体晶片的源极/漏极注入，在半导体晶片上形成覆盖层，并执行源极/漏极退火。此外，该方法包括执行盖层的损伤注入并去除半导体晶片上的覆盖层。

6. 发明申请

US20070196991A1 SEMICONDUCTOR DEVICE HAVING A STRAIN INDUCING SIDEWALL SPACER AND A METHOD OF MANUFACTURE THEREFOR 审中-公开
标题翻译：具有感应平台间隙的应变的半导体器件及其制造方法
公开(公告)号：US20070196991A1
公开(公告)日：2007-08-23
申请号：US11610908
申请日：2006-12-14
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Mehta , Lahir Adam
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Mehta , Lahir Adam
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L29/6656 , H01L29/7843
摘要： The present invention provides a method for manufacturing a semiconductor device as well as a semiconductor device. The method, among other steps, may include forming a gate structure over a substrate, and forming a strain inducing sidewall spacer proximate a sidewall of the gate structure, the strain inducing sidewall configured to introduce strain in a channel region below the gate structure.
摘要翻译：本发明提供一种半导体器件的制造方法以及半导体器件。除了其他步骤之外，该方法可以包括在衬底上形成栅极结构，以及在栅极结构的侧壁附近形成应变诱导侧壁间隔，所述应变诱导侧壁被配置为在栅极结构下方的沟道区域中引入应变。

7. 发明授权

US08659112B2 Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit 有权
标题翻译：在集成电路上选择PMOS晶体管的碳氮掺杂
公开(公告)号：US08659112B2
公开(公告)日：2014-02-25
申请号：US12967109
申请日：2010-12-14
申请人： Mahalingam Nandakumar , Amitabh Jain
发明人： Mahalingam Nandakumar , Amitabh Jain
IPC分类号： H01L21/70 , H01L27/088 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28202 , H01L21/823418 , H01L21/823462 , H01L29/1083 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.
摘要翻译：形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。在源极和漏极之间进行源极/漏极退火。

8. 发明申请

US20090166675A1 STRAIN ENGINEERING IN SEMICONDUCTOR COMPONENTS 审中-公开
标题翻译：半导体器件中的应变工程
公开(公告)号：US20090166675A1
公开(公告)日：2009-07-02
申请号：US12346458
申请日：2008-12-30
申请人： Mahalingam Nandakumar
发明人： Mahalingam Nandakumar
IPC分类号： H01L29/737 , H01L21/265 , H01L21/337
CPC分类号： H01L21/02658 , H01L21/02667
摘要： This disclosure relates to strain engineering to improve the performance of semiconductor components that include a strained region of the semiconductor substrate. The disclosure involves the amorphization of the target region and the recrystallization of the atomic lattice whilst imposing a strain on the region. The region so formed will form a strained lattice, wherein the strain is uniformly distributed throughout the region, and which retains the intrinsic strain even if the source of the mechanical strain is removed. The disclosure includes methods for forming semiconductor substrates having strained regions (such as semiconductor components having a strained channel region) and semiconductor components formed thereby, as well as variations having various properties and advantages.
摘要翻译：本公开涉及应变工程，以改善包括半导体衬底的应变区域的半导体部件的性能。本公开涉及目标区域的非晶化和原子格子的再结晶，同时在该区域上施加应变。这样形成的区域将形成应变格子，其中应变均匀地分布在整个区域中，并且即使去除了机械应变源，其也保留了本征应变。本公开包括用于形成具有应变区域（例如具有应变通道区域的半导体部件）和由其形成的半导体部件的半导体衬底的方法以及具有各种性质和优点的变型。

9. 发明授权

US07393787B2 Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment 有权
标题翻译：使用高温化学处理形成其中具有均匀氮分布的含氮介电层
公开(公告)号：US07393787B2
公开(公告)日：2008-07-01
申请号：US11209140
申请日：2005-08-22
申请人： Hiroaki Niimi , Reima T. Laaksonen , Mahalingam Nandakumar
发明人： Hiroaki Niimi , Reima T. Laaksonen , Mahalingam Nandakumar
IPC分类号： H01L21/302
CPC分类号： H01L27/11 , H01L21/823462 , H01L21/823857 , H01L21/8249
摘要： The present invention provides a method for manufacturing a gate dielectric, a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit. The method for manufacturing the gate dielectric, without limitation, may include forming a nitrided dielectric layer (520) over a substrate (310), the nitrided dielectric layer (520) having a non-uniformity of nitrogen in a bulk thereof, and removing at least a portion of the nitrided dielectric layer (520) using a high temperature chemical treatment, the removing reducing the non-uniformity.
摘要翻译：本发明提供一种栅极电介质的制造方法，半导体器件的制造方法以及集成电路的制造方法。用于制造栅极电介质的方法，但不限于，可以包括在衬底（310）上形成氮化介电层（520），氮化介电层（520）在其主体中具有不均匀的氮，并且在使用高温化学处理的氮化介电层（520）的至少一部分，去除减少不均匀性。

10. 发明授权

US06228725B1 Semiconductor devices with pocket implant and counter doping 有权
标题翻译：具有袋式注入和反掺杂的半导体器件
公开(公告)号：US06228725B1
公开(公告)日：2001-05-08
申请号：US09281543
申请日：1999-03-30
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/7838
摘要： A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).
摘要翻译：形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

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