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1. 发明授权

US5885861A Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor 失效
标题翻译：通过将杂质共注入晶体管栅极导体来减少掺杂剂扩散
公开(公告)号：US5885861A
公开(公告)日：1999-03-23
申请号：US865883
申请日：1997-05-30
申请人： Mark I. Gardner , H. Jim Fulford , Derrick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derrick J. Wristers
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/08 , H01L29/49
CPC分类号： H01L21/28185 , H01L21/28035 , H01L21/28176 , H01L21/823814 , H01L21/823828 , H01L29/0847 , H01L29/4916 , H01L29/6659 , H01L21/26506 , H01L21/28211 , Y10S257/914 , Y10S438/918
摘要： Diffusion of dopants within the gate of the transistor and/or the source/drain regions can be inhibited by the ion co-implantation of impurities in addition to the ion implantation of the n-type or p-type dopants. Implanting a combination of nitrogen and carbon for p-type devices in addition to the p-type dopants and implanting a combination of nitrogen and fluorine for n-type devices in addition to the n-type dopants, significantly reduces the diffusion of the n-type and p-type dopants. The co-implantation of the additional impurities may be performed before patterning of the polysilicon layer to yield the gate conductors. The impurities may be implanted first, followed by the n-type or p-type dopants. Additional implantation of the impurities may be performed after the patterning of the polysilicon layer in order to reduce dopant diffusion in the source and drain regions. The ion implantation of the gate conductors and source/drain regions may performed at the same time following the patterning of the polysilicon layer.
摘要翻译：除了n型或p型掺杂剂的离子注入之外，通过杂质的离子共注入可以抑制晶体管和/或源/漏区的栅极内的掺杂剂的扩散。除了n型掺杂剂之外，除了p型掺杂剂之外，还植入用于p型器件的氮和碳的组合，并且除了n型掺杂剂之外，为n型器件注入氮和氟的组合，型和p型掺杂剂。附加杂质的共同注入可以在图案化多晶硅层之前进行以产生栅极导体。首先可以注入杂质，其次是n型或p型掺杂剂。可以在图案化多晶硅层之后进行杂质的附加注入，以便减少源极和漏极区域中的掺杂剂扩散。栅极导体和源极/漏极区域的离子注入可以在多晶硅层的图案化之后的同时进行。

2. 发明授权

US5930620A Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures 失效
标题翻译：在浅沟槽隔离结构的边缘处的栅极电介质击穿电阻
公开(公告)号：US5930620A
公开(公告)日：1999-07-27
申请号：US928619
申请日：1997-09-12
申请人： Derrick J. Wristers , Mark I. Gardner , H. Jim Fulford
发明人： Derrick J. Wristers , Mark I. Gardner , H. Jim Fulford
IPC分类号： H01L21/762 , H01L29/423 , H01L21/8242 , H01L21/265 , H01L21/31 , H01L21/469 , H01L21/76
CPC分类号： H01L21/76235 , H01L29/42368 , Y10S438/981
摘要： A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the portions relative to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, the first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate. The increased oxide thickness adjacent to the discontinuities of the isolation trench reduces the electric field across the oxide.
摘要翻译：一种在半导体衬底中形成至少一个隔离结构的半导体工艺。将含氧物质引入到靠近隔离结构的半导体衬底的部分中。然后在半导体衬底的上表面上形成栅介质层。在半导体衬底的近端部分存在含氧物质会增加部分相对于远离隔离结构的衬底部分的氧化速率的氧化速率。以这种方式，在半导体衬底的近端部分上的栅极电介质的第一厚度大于半导体衬底的剩余部分上的栅极氧化物层的第二厚度。与隔离沟槽的不连续性相邻的增加的氧化物厚度减小了跨过氧化物的电场。

3. 发明授权

US5904517A Ultra thin high K spacer material for use in transistor fabrication 失效
标题翻译：用于晶体管制造的超薄高K隔离材料
公开(公告)号：US5904517A
公开(公告)日：1999-05-18
申请号：US112529
申请日：1998-07-08
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Derrick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Derrick J. Wristers
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/49 , H01L21/70
CPC分类号： H01L29/6659 , H01L21/823468 , H01L29/4983 , H01L29/665
摘要： A fabrication process and integrated circuit formed thereby are provided in which relatively thin sidewall spacers extend laterally from opposed sidewall surfaces of a transistor gate conductor. The present invention contemplates forming a gate structure upon a semiconductor substrate. Lightly doped drain impurity areas may be formed in the semiconductor substrate aligned with sidewall of the gate structure. An oxygen-containing dielectric layer is deposited upon the semiconductor topography, followed by deposition of an oxidizable metal upon the dielectric layer. The oxygen-containing dielectric and the oxidizable metal are thermally annealed such that metal oxide spacers are formed adjacent sidewall surfaces of the gate structure. In an embodiment, portions of the dielectric and the metal are selectively removed prior to the anneal. In an alternate embodiment, the metal and the dielectric are annealed first, followed by selective removal of portions of the resulting metal oxide. Following spacer formation, source and drain impurity areas may be formed in the semiconductor substrate aligned with sidewall surfaces of the spacers. A metal silicide may be formed upon upper surfaces of the gate conductor and the source and drain impurity areas.
摘要翻译：提供了由此形成的制造工艺和集成电路，其中较薄的侧壁间隔件从晶体管栅极导体的相对的侧壁表面横向延伸。本发明考虑在半导体衬底上形成栅极结构。可以在与栅极结构的侧壁对准的半导体衬底中形成轻掺杂的漏极杂质区域。在半导体形貌上沉积含氧介电层，然后在电介质层上沉积可氧化金属。含氧电介质和可氧化金属被热退火，使得邻近栅极结构的侧壁表面形成金属氧化物间隔物。在一个实施例中，电介质和金属的部分在退火之前被选择性地去除。在替代实施例中，首先对金属和电介质进行退火，然后选择性地去除所得到的金属氧化物的一部分。在间隔物形成之后，源极和漏极杂质区域可以形成在与间隔物的侧壁表面对准的半导体衬底中。可以在栅极导体的上表面和源极和漏极杂质区域上形成金属硅化物。

4. 发明授权

US06225201B1 Ultra short transistor channel length dictated by the width of a sidewall spacer 失效
标题翻译：超短晶体管通道长度由侧壁间隔物的宽度决定
公开(公告)号：US06225201B1
公开(公告)日：2001-05-01
申请号：US09433801
申请日：1999-11-03
申请人： Mark I. Gardner , Derrick J. Wristers , Jon D. Cheek , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Derrick J. Wristers , Jon D. Cheek , Thomas E. Spikes, Jr.
IPC分类号： H01L213205
CPC分类号： H01L29/517 , H01L21/0338 , H01L21/28114 , H01L21/28132 , H01L21/2815 , H01L21/28194 , H01L21/31144 , H01L29/6659 , H01L29/66659 , Y10S438/947
摘要： An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length dictated by the width of a sidewall spacer which either embodies a gate conductor for the transistor or is used to pattern an underlying gate conductor. In one embodiment, the sidewall spacers are formed upon and extending laterally from the opposed sidewall surfaces of a sacrificial material. The sidewall surfaces of the sacrificial material are defined by forming the sacrificial material within an opening interposed laterally between vertically extending sidewalls which bound a gate dielectric. An upper portion of the gate dielectric is removed to partially expose the sidewall surfaces arranged at the periphery of the sacrificial material. Polysilicon spacers are formed exclusively upon the sidewall surfaces of the sacrificial material to define a pair of gate conductors having relatively small lateral widths. Portions of the gate dielectric not arranged exclusively beneath the gate conductors may be selectively removed. In another embodiment, sidewall spacers are used to protect select regions of a polysilicon gate material arranged exclusively underneath the spacers from being etched. The sidewall spacers are formed upon and extending laterally from sidewall surfaces arranged at the periphery of an opening which extends through a masking or sacrificial material to an underlying polysilicon gate material. The sidewall spacers are sacrificial in that they are removed from the semiconductor topography after they have served their purpose of masking the underlying polysilicon gate material.
摘要翻译：提供了一种集成电路制造工艺，用于形成具有由侧壁间隔物的宽度所规定的超短沟道长度的晶体管，该侧壁间隔物体现了晶体管的栅极导体或用于对下面的栅极导体进行图案化。在一个实施例中，侧壁间隔件形成在牺牲材料的相对的侧壁表面上并从牺牲材料的相对侧壁表面延伸。牺牲材料的侧壁表面通过在封闭栅极电介质的垂直延伸侧壁之间横向插入的开口内形成牺牲材料来限定。去除栅极电介质的上部以部分地暴露设置在牺牲材料的周边处的侧壁表面。专门在牺牲材料的侧壁表面上形成多晶硅间隔物，以限定具有相对小的横向宽度的一对栅极导体。可以选择性地去除不排列在栅极导体下方的栅极电介质的部分。在另一个实施例中，侧壁间隔件用于保护专门在间隔物下方布置的多晶硅栅极材料的选择区域被蚀刻。侧壁间隔件形成在侧壁表面上并且从侧壁表面延伸出来，该侧壁表面布置在开口的周边，该开口延伸穿过掩模或牺牲材料到下面的多晶硅栅极材料。侧壁间隔物是牺牲的，因为它们已经用于掩盖下面的多晶硅栅极材料的目的，从半导体拓扑图中去除它们。

5. 发明授权

US5899721A Method of based spacer formation for ultra-small sapcer geometries 失效
标题翻译：用于超小间隔物几何形状的抛光间隔物形成方法
公开(公告)号：US5899721A
公开(公告)日：1999-05-04
申请号：US36744
申请日：1998-03-09
申请人： Mark I. Gardner , Derrick J. Wristers
发明人： Mark I. Gardner , Derrick J. Wristers
IPC分类号： H01L21/336 , H01L29/49
CPC分类号： H01L29/6659 , H01L29/4983 , H01L29/665
摘要： A transistor and transistor fabrication method are presented wherein ultra small spacers are formed adjacent sidewall surfaces of a gate conductor. A first dielectric material is deposited over a semiconductor topography. The first dielectric is partially removed to expose a portion of the gate conductor, and a second dielectric material is deposited upon the first dielectric material and the gate conductor. The second dielectric material is anisotropically etched such that the second dielectric material is preferentially removed from substantially horizontal surfaces and retained adjacent substantially vertical surfaces. The first dielectric material is then selectively removed from areas not masked by the second dielectric material. The composite spacers thus formed adjacent sidewall surfaces of the gate conductor are thinner than spacers formed using conventional techniques. Sub-0.25-micron transistors having sidewall spacers formed by the process described herein may be less susceptible to deleterious source-side parasitic resistance than transistors having conventionally formed spacers.
摘要翻译：提出了一种晶体管和晶体管制造方法，其中在栅极导体的侧壁表面附近形成超小间隔物。第一介电材料沉积在半导体形貌上。部分去除第一电介质以露出栅极导体的一部分，并且第二电介质材料沉积在第一电介质材料和栅极导体上。第二电介质材料被各向异性地蚀刻，使得第二电介质材料优先从基本上水平的表面移除并且保持相邻的基本垂直的表面。然后从未被第二介电材料掩蔽的区域中选择性地去除第一电介质材料。由此形成在栅极导体的相邻侧壁表面的复合间隔物比使用常规技术形成的间隔物更薄。具有通过本文所述方法形成的侧壁间隔物的次0.25微米晶体管可能比具有常规形成的间隔物的晶体管更不易受到有害的源极寄生电阻的影响。

6. 发明授权

US6162692A Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor 失效
标题翻译：扩散阻挡层和反掺杂剂区域的集成，以保持晶体管结的掺杂剂水平
公开(公告)号：US6162692A
公开(公告)日：2000-12-19
申请号：US105721
申请日：1998-06-26
申请人： Mark I. Gardner , Derrick J. Wristers , Thien T. Nguyen
发明人： Mark I. Gardner , Derrick J. Wristers , Thien T. Nguyen
IPC分类号： H01L21/265 , H01L21/336 , H01L21/425
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/66659
摘要： An integrated circuit fabrication process is provided for placing a diffusion barrier layer above the junctions of a transistor and counter dopant regions at the boundaries of the junctions to enhance the dopant level within the junctions. The diffusion barrier layer (e.g., a nitride layer) is strategically placed between the junctions and sidewall spacers which extend laterally from the opposed sidewall surfaces of a gate conductor. The diffusion barrier layer inhibits the dopants within the junctions from passing into the sidewall spacers. Dopant species opposite in type to those in the junctions are implanted into the counter dopant regions using a "large tilt angle" (LTA) implant methodology, wherein the angle of incidence of the injected dopant ions is at a non-perpendicular angle relative to the upper surface of the semiconductor substrate. In this manner, the counter dopant regions are placed both beneath the junctions and at the juncture between the junctions and the channel region of the transistor. The counter dopants fill vacancy and interstitial sites within the substrate, and thus block migration avenues through which the dopants in the junctions could otherwise pass into other areas of the substrate. The integration of the diffusion barrier layer with the counter dopant regions ensures that the dopant concentration within the junctions will be maintained.
摘要翻译：提供集成电路制造工艺，用于在结点的边界处的晶体管和反掺杂剂区域的结的上方放置扩散阻挡层，以增强接合处的掺杂剂水平。策略性地将扩散阻挡层（例如，氮化物层）放置在从栅极导体的相对的侧壁表面横向延伸的接头和侧壁间隔件之间。扩散阻挡层抑制接合处的掺杂剂进入侧壁间隔物。使用“大倾斜角”（LTA）植入方法将类型与接合点相反的掺杂物质注入到反掺杂剂区域中，其中注入的掺杂剂离子的入射角相对于半导体衬底的上表面。以这种方式，反掺杂剂区域被放置在结点之下并且在晶体管的结和沟道区之间的接合处。反掺杂剂填充衬底内的空位和间隙位置，因此阻挡迁移通道，通过该途径掺杂剂可以通过其途径进入衬底的其它区域。扩散阻挡层与反掺杂剂区域的集成确保了连接处的掺杂剂浓度将得到保持。

7. 发明授权

US06552776B1 Photolithographic system including light filter that compensates for lens error 有权
标题翻译：光刻系统包括补偿透镜误差的滤光片
公开(公告)号：US06552776B1
公开(公告)日：2003-04-22
申请号：US09183176
申请日：1998-10-30
申请人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
发明人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
IPC分类号： G03B2754
CPC分类号： G03F7/70558 , G03F7/70191 , G03F7/706
摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.
摘要翻译：公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化数据以提供所需的光强度变化。本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。

8. 发明授权

US06531364B1 Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer 有权
标题翻译：使用牺牲多晶硅种子层形成超薄栅极电介质的先进制造技术
公开(公告)号：US06531364B1
公开(公告)日：2003-03-11
申请号：US09129703
申请日：1998-08-05
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/28211 , H01L29/513 , H01L29/518
摘要： A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial polysilicon layer is preferably undertaken by oxidizing a portion of the sacrificial polysilicon layer and then etching the oxidized portion. As an option, the sacrificial polysilicon layer may be heated such that it is recrystallized. The sacrificial polysilicon layer is preferably annealed in a nitrogen-bearing ambient such that it is converted to a gate dielectric layer that includes nitride. Polysilicon may be deposited upon the gate dielectric layer, and select portions of the polysilicon may be removed to form a gate conductor. LDD and source/drain areas may be formed adjacent to the gate conductor.
摘要翻译：提出了一种用于形成晶体管的方法，其中多晶硅优选沉积在介电覆盖的衬底上以形成牺牲多晶硅层。然后可以将牺牲多晶硅层还原成所需的厚度。牺牲多晶硅层的厚度减少优选通过氧化牺牲多晶硅层的一部分然后蚀刻氧化部分进行。作为选择，可以加热牺牲多晶硅层使其重结晶。牺牲多晶硅层优选在含氮环境中退火，使得其被转换成包括氮化物的栅极电介质层。多晶硅可以沉积在栅极介电层上，并且可以去除多晶硅的部分以形成栅极导体。 LDD和源极/漏极区域可以形成在栅极导体附近。

9. 发明授权

US06303962B1 Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures 有权
标题翻译：具有低电阻金属源和漏极的绝缘隔离晶体管，使用牺牲源极和漏极结构形成
公开(公告)号：US06303962B1
公开(公告)日：2001-10-16
申请号：US09227512
申请日：1999-01-06
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： A01L2701
CPC分类号： H01L29/66757 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/41733 , H01L29/78675
摘要： A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The transistor channel is located in a polysilicon layer arranged over a dielectric layer on a semiconductor substrate. To fabricate the transistor, an isolating dielectric, polysilicon layer, and protective dielectric layer are deposited over a semiconductor substrate. Source/drain trenches are formed in the protective dielectric and polysilicon layers and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which may be formed from a low-resistance metal. The resulting transistor may exhibit low contact and series resistances, and increased operation speed.
摘要翻译：在金属氧化物半导体（MOS）工艺中，使用自对准的低电阻源极和漏极区域提供并形成晶体管。晶体管的栅极也可以由诸如金属的低电阻材料形成。晶体管沟道位于布置在半导体衬底上的电介质层上的多晶硅层中。为了制造晶体管，在半导体衬底上沉积隔离电介质，多晶硅层和保护电介质层。源极/漏极沟槽形成在保护电介质层和多晶硅层中，随后填充有牺牲电介质。位于这些牺牲电介质之间的保护电介质被去除，并被替代为可由低电阻金属形成的侧壁间隔物，栅极电介质和栅极导体。随后去除牺牲电介质并用可由低电阻金属形成的源极/漏极区域代替。所得到的晶体管可以表现出低接触和串联电阻，并且增加了操作速度。

10. 发明授权

US06255698B1 Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit 有权
标题翻译：在集成电路中分别优化了n沟道和p沟道晶体管的栅极结构
公开(公告)号：US06255698B1
公开(公告)日：2001-07-03
申请号：US09301263
申请日：1999-04-28
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L2976
CPC分类号： H01L21/823842 , H01L29/66545
摘要： An integrated circuit containing separately optimized gate structures for n-channel and p-channel transistors is provided and formed. Original gate structures for both n-channel and p-channel transistors are patterned over appropriately-doped active regions of a semiconductor substrate. Protective dielectrics are formed over the semiconductor substrate to the same elevation level as the upper surfaces of the original gate structures, so that only the upper surfaces of the gate structures are exposed. A masking layer is used to cover the gate structures of either the p-channel or the n-channel transistors. The uncovered gate structures are removed, forming a trench within the protective dielectric in place of each removed gate structure. The trenches are refilled with a new gate structure which is preferably optimized for operation of the appropriate transistor type (n-channel or p-channel).
摘要翻译：提供并形成了包含用于n沟道和p沟道晶体管的单独优化的栅极结构的集成电路。用于n沟道和p沟道晶体管的原始栅极结构在半导体衬底的适当掺杂的有源区上被图案化。在半导体衬底上形成与原始栅极结构的上表面相同的高度水平面的保护电介质，使得只有栅极结构的上表面露出。掩模层用于覆盖p沟道或n沟道晶体管的栅极结构。去除未覆盖的栅极结构，在保护电介质内形成沟槽，代替每个去除的栅极结构。沟槽用新的栅极结构重新填充，该栅极结构优选地适合于适当的晶体管类型（n沟道或p沟道）的操作。

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