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1. 发明授权

US6162692A Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor 失效
标题翻译：扩散阻挡层和反掺杂剂区域的集成，以保持晶体管结的掺杂剂水平
公开(公告)号：US6162692A
公开(公告)日：2000-12-19
申请号：US105721
申请日：1998-06-26
申请人： Mark I. Gardner , Derrick J. Wristers , Thien T. Nguyen
发明人： Mark I. Gardner , Derrick J. Wristers , Thien T. Nguyen
IPC分类号： H01L21/265 , H01L21/336 , H01L21/425
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/66659
摘要： An integrated circuit fabrication process is provided for placing a diffusion barrier layer above the junctions of a transistor and counter dopant regions at the boundaries of the junctions to enhance the dopant level within the junctions. The diffusion barrier layer (e.g., a nitride layer) is strategically placed between the junctions and sidewall spacers which extend laterally from the opposed sidewall surfaces of a gate conductor. The diffusion barrier layer inhibits the dopants within the junctions from passing into the sidewall spacers. Dopant species opposite in type to those in the junctions are implanted into the counter dopant regions using a "large tilt angle" (LTA) implant methodology, wherein the angle of incidence of the injected dopant ions is at a non-perpendicular angle relative to the upper surface of the semiconductor substrate. In this manner, the counter dopant regions are placed both beneath the junctions and at the juncture between the junctions and the channel region of the transistor. The counter dopants fill vacancy and interstitial sites within the substrate, and thus block migration avenues through which the dopants in the junctions could otherwise pass into other areas of the substrate. The integration of the diffusion barrier layer with the counter dopant regions ensures that the dopant concentration within the junctions will be maintained.
摘要翻译：提供集成电路制造工艺，用于在结点的边界处的晶体管和反掺杂剂区域的结的上方放置扩散阻挡层，以增强接合处的掺杂剂水平。策略性地将扩散阻挡层（例如，氮化物层）放置在从栅极导体的相对的侧壁表面横向延伸的接头和侧壁间隔件之间。扩散阻挡层抑制接合处的掺杂剂进入侧壁间隔物。使用“大倾斜角”（LTA）植入方法将类型与接合点相反的掺杂物质注入到反掺杂剂区域中，其中注入的掺杂剂离子的入射角相对于半导体衬底的上表面。以这种方式，反掺杂剂区域被放置在结点之下并且在晶体管的结和沟道区之间的接合处。反掺杂剂填充衬底内的空位和间隙位置，因此阻挡迁移通道，通过该途径掺杂剂可以通过其途径进入衬底的其它区域。扩散阻挡层与反掺杂剂区域的集成确保了连接处的掺杂剂浓度将得到保持。

2. 发明授权

US06225201B1 Ultra short transistor channel length dictated by the width of a sidewall spacer 失效
标题翻译：超短晶体管通道长度由侧壁间隔物的宽度决定
公开(公告)号：US06225201B1
公开(公告)日：2001-05-01
申请号：US09433801
申请日：1999-11-03
申请人： Mark I. Gardner , Derrick J. Wristers , Jon D. Cheek , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Derrick J. Wristers , Jon D. Cheek , Thomas E. Spikes, Jr.
IPC分类号： H01L213205
CPC分类号： H01L29/517 , H01L21/0338 , H01L21/28114 , H01L21/28132 , H01L21/2815 , H01L21/28194 , H01L21/31144 , H01L29/6659 , H01L29/66659 , Y10S438/947
摘要： An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length dictated by the width of a sidewall spacer which either embodies a gate conductor for the transistor or is used to pattern an underlying gate conductor. In one embodiment, the sidewall spacers are formed upon and extending laterally from the opposed sidewall surfaces of a sacrificial material. The sidewall surfaces of the sacrificial material are defined by forming the sacrificial material within an opening interposed laterally between vertically extending sidewalls which bound a gate dielectric. An upper portion of the gate dielectric is removed to partially expose the sidewall surfaces arranged at the periphery of the sacrificial material. Polysilicon spacers are formed exclusively upon the sidewall surfaces of the sacrificial material to define a pair of gate conductors having relatively small lateral widths. Portions of the gate dielectric not arranged exclusively beneath the gate conductors may be selectively removed. In another embodiment, sidewall spacers are used to protect select regions of a polysilicon gate material arranged exclusively underneath the spacers from being etched. The sidewall spacers are formed upon and extending laterally from sidewall surfaces arranged at the periphery of an opening which extends through a masking or sacrificial material to an underlying polysilicon gate material. The sidewall spacers are sacrificial in that they are removed from the semiconductor topography after they have served their purpose of masking the underlying polysilicon gate material.
摘要翻译：提供了一种集成电路制造工艺，用于形成具有由侧壁间隔物的宽度所规定的超短沟道长度的晶体管，该侧壁间隔物体现了晶体管的栅极导体或用于对下面的栅极导体进行图案化。在一个实施例中，侧壁间隔件形成在牺牲材料的相对的侧壁表面上并从牺牲材料的相对侧壁表面延伸。牺牲材料的侧壁表面通过在封闭栅极电介质的垂直延伸侧壁之间横向插入的开口内形成牺牲材料来限定。去除栅极电介质的上部以部分地暴露设置在牺牲材料的周边处的侧壁表面。专门在牺牲材料的侧壁表面上形成多晶硅间隔物，以限定具有相对小的横向宽度的一对栅极导体。可以选择性地去除不排列在栅极导体下方的栅极电介质的部分。在另一个实施例中，侧壁间隔件用于保护专门在间隔物下方布置的多晶硅栅极材料的选择区域被蚀刻。侧壁间隔件形成在侧壁表面上并且从侧壁表面延伸出来，该侧壁表面布置在开口的周边，该开口延伸穿过掩模或牺牲材料到下面的多晶硅栅极材料。侧壁间隔物是牺牲的，因为它们已经用于掩盖下面的多晶硅栅极材料的目的，从半导体拓扑图中去除它们。

3. 发明授权

US5885861A Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor 失效
标题翻译：通过将杂质共注入晶体管栅极导体来减少掺杂剂扩散
公开(公告)号：US5885861A
公开(公告)日：1999-03-23
申请号：US865883
申请日：1997-05-30
申请人： Mark I. Gardner , H. Jim Fulford , Derrick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derrick J. Wristers
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/08 , H01L29/49
CPC分类号： H01L21/28185 , H01L21/28035 , H01L21/28176 , H01L21/823814 , H01L21/823828 , H01L29/0847 , H01L29/4916 , H01L29/6659 , H01L21/26506 , H01L21/28211 , Y10S257/914 , Y10S438/918
摘要： Diffusion of dopants within the gate of the transistor and/or the source/drain regions can be inhibited by the ion co-implantation of impurities in addition to the ion implantation of the n-type or p-type dopants. Implanting a combination of nitrogen and carbon for p-type devices in addition to the p-type dopants and implanting a combination of nitrogen and fluorine for n-type devices in addition to the n-type dopants, significantly reduces the diffusion of the n-type and p-type dopants. The co-implantation of the additional impurities may be performed before patterning of the polysilicon layer to yield the gate conductors. The impurities may be implanted first, followed by the n-type or p-type dopants. Additional implantation of the impurities may be performed after the patterning of the polysilicon layer in order to reduce dopant diffusion in the source and drain regions. The ion implantation of the gate conductors and source/drain regions may performed at the same time following the patterning of the polysilicon layer.
摘要翻译：除了n型或p型掺杂剂的离子注入之外，通过杂质的离子共注入可以抑制晶体管和/或源/漏区的栅极内的掺杂剂的扩散。除了n型掺杂剂之外，除了p型掺杂剂之外，还植入用于p型器件的氮和碳的组合，并且除了n型掺杂剂之外，为n型器件注入氮和氟的组合，型和p型掺杂剂。附加杂质的共同注入可以在图案化多晶硅层之前进行以产生栅极导体。首先可以注入杂质，其次是n型或p型掺杂剂。可以在图案化多晶硅层之后进行杂质的附加注入，以便减少源极和漏极区域中的掺杂剂扩散。栅极导体和源极/漏极区域的离子注入可以在多晶硅层的图案化之后的同时进行。

4. 发明授权

US5899721A Method of based spacer formation for ultra-small sapcer geometries 失效
标题翻译：用于超小间隔物几何形状的抛光间隔物形成方法
公开(公告)号：US5899721A
公开(公告)日：1999-05-04
申请号：US36744
申请日：1998-03-09
申请人： Mark I. Gardner , Derrick J. Wristers
发明人： Mark I. Gardner , Derrick J. Wristers
IPC分类号： H01L21/336 , H01L29/49
CPC分类号： H01L29/6659 , H01L29/4983 , H01L29/665
摘要： A transistor and transistor fabrication method are presented wherein ultra small spacers are formed adjacent sidewall surfaces of a gate conductor. A first dielectric material is deposited over a semiconductor topography. The first dielectric is partially removed to expose a portion of the gate conductor, and a second dielectric material is deposited upon the first dielectric material and the gate conductor. The second dielectric material is anisotropically etched such that the second dielectric material is preferentially removed from substantially horizontal surfaces and retained adjacent substantially vertical surfaces. The first dielectric material is then selectively removed from areas not masked by the second dielectric material. The composite spacers thus formed adjacent sidewall surfaces of the gate conductor are thinner than spacers formed using conventional techniques. Sub-0.25-micron transistors having sidewall spacers formed by the process described herein may be less susceptible to deleterious source-side parasitic resistance than transistors having conventionally formed spacers.
摘要翻译：提出了一种晶体管和晶体管制造方法，其中在栅极导体的侧壁表面附近形成超小间隔物。第一介电材料沉积在半导体形貌上。部分去除第一电介质以露出栅极导体的一部分，并且第二电介质材料沉积在第一电介质材料和栅极导体上。第二电介质材料被各向异性地蚀刻，使得第二电介质材料优先从基本上水平的表面移除并且保持相邻的基本垂直的表面。然后从未被第二介电材料掩蔽的区域中选择性地去除第一电介质材料。由此形成在栅极导体的相邻侧壁表面的复合间隔物比使用常规技术形成的间隔物更薄。具有通过本文所述方法形成的侧壁间隔物的次0.25微米晶体管可能比具有常规形成的间隔物的晶体管更不易受到有害的源极寄生电阻的影响。

5. 发明授权

US5930620A Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures 失效
标题翻译：在浅沟槽隔离结构的边缘处的栅极电介质击穿电阻
公开(公告)号：US5930620A
公开(公告)日：1999-07-27
申请号：US928619
申请日：1997-09-12
申请人： Derrick J. Wristers , Mark I. Gardner , H. Jim Fulford
发明人： Derrick J. Wristers , Mark I. Gardner , H. Jim Fulford
IPC分类号： H01L21/762 , H01L29/423 , H01L21/8242 , H01L21/265 , H01L21/31 , H01L21/469 , H01L21/76
CPC分类号： H01L21/76235 , H01L29/42368 , Y10S438/981
摘要： A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the portions relative to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, the first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate. The increased oxide thickness adjacent to the discontinuities of the isolation trench reduces the electric field across the oxide.
摘要翻译：一种在半导体衬底中形成至少一个隔离结构的半导体工艺。将含氧物质引入到靠近隔离结构的半导体衬底的部分中。然后在半导体衬底的上表面上形成栅介质层。在半导体衬底的近端部分存在含氧物质会增加部分相对于远离隔离结构的衬底部分的氧化速率的氧化速率。以这种方式，在半导体衬底的近端部分上的栅极电介质的第一厚度大于半导体衬底的剩余部分上的栅极氧化物层的第二厚度。与隔离沟槽的不连续性相邻的增加的氧化物厚度减小了跨过氧化物的电场。

6. 发明授权

US5904517A Ultra thin high K spacer material for use in transistor fabrication 失效
标题翻译：用于晶体管制造的超薄高K隔离材料
公开(公告)号：US5904517A
公开(公告)日：1999-05-18
申请号：US112529
申请日：1998-07-08
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Derrick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Derrick J. Wristers
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/49 , H01L21/70
CPC分类号： H01L29/6659 , H01L21/823468 , H01L29/4983 , H01L29/665
摘要： A fabrication process and integrated circuit formed thereby are provided in which relatively thin sidewall spacers extend laterally from opposed sidewall surfaces of a transistor gate conductor. The present invention contemplates forming a gate structure upon a semiconductor substrate. Lightly doped drain impurity areas may be formed in the semiconductor substrate aligned with sidewall of the gate structure. An oxygen-containing dielectric layer is deposited upon the semiconductor topography, followed by deposition of an oxidizable metal upon the dielectric layer. The oxygen-containing dielectric and the oxidizable metal are thermally annealed such that metal oxide spacers are formed adjacent sidewall surfaces of the gate structure. In an embodiment, portions of the dielectric and the metal are selectively removed prior to the anneal. In an alternate embodiment, the metal and the dielectric are annealed first, followed by selective removal of portions of the resulting metal oxide. Following spacer formation, source and drain impurity areas may be formed in the semiconductor substrate aligned with sidewall surfaces of the spacers. A metal silicide may be formed upon upper surfaces of the gate conductor and the source and drain impurity areas.
摘要翻译：提供了由此形成的制造工艺和集成电路，其中较薄的侧壁间隔件从晶体管栅极导体的相对的侧壁表面横向延伸。本发明考虑在半导体衬底上形成栅极结构。可以在与栅极结构的侧壁对准的半导体衬底中形成轻掺杂的漏极杂质区域。在半导体形貌上沉积含氧介电层，然后在电介质层上沉积可氧化金属。含氧电介质和可氧化金属被热退火，使得邻近栅极结构的侧壁表面形成金属氧化物间隔物。在一个实施例中，电介质和金属的部分在退火之前被选择性地去除。在替代实施例中，首先对金属和电介质进行退火，然后选择性地去除所得到的金属氧化物的一部分。在间隔物形成之后，源极和漏极杂质区域可以形成在与间隔物的侧壁表面对准的半导体衬底中。可以在栅极导体的上表面和源极和漏极杂质区域上形成金属硅化物。

7. 发明授权

US06281132B1 Device and method for etching nitride spacers formed upon an integrated circuit gate conductor 有权
标题翻译：用于蚀刻形成在集成电路栅极导体上的氮化物间隔物的装置和方法
公开(公告)号：US06281132B1
公开(公告)日：2001-08-28
申请号：US09167622
申请日：1998-10-06
申请人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
发明人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
IPC分类号： H01L213065
CPC分类号： H01L21/31116
摘要： A dry etch method is presented wherein a semiconductor substrate is introduced between a first electrode and a second electrode maintained within a reaction chamber. In this method, a main etch step is performed in which a first quantity of low frequency power is applied to the pair of electrodes from an RF power source. A first gas flow is circulated through the reaction chamber during the application of power. This first gas flow includes a first argon flow, a first oxygen flow, and a first fluorocarbon flow. Applying the first quantity of low frequency power creates a first plasma for etching a portion of a nitride layer arranged above the semiconductor substrate.
摘要翻译：提出了一种干蚀刻方法，其中将半导体衬底引入到保持在反应室内的第一电极和第二电极之间。在该方法中，执行主要蚀刻步骤，其中从RF电源向第一对电极施加第一数量的低频功率。在施加电力期间，第一气流在反应室中循环。该第一气流包括第一氩气流，第一氧气流和第一碳氟化合物流。施加第一量的低频功率产生第一等离子体，用于蚀刻布置在半导体衬底上方的氮化物层的一部分。

8. 发明授权

US06248252B1 Method of fabricating sub-micron metal lines 有权
标题翻译：制造亚微米金属线的方法
公开(公告)号：US06248252B1
公开(公告)日：2001-06-19
申请号：US09256541
申请日：1999-02-24
申请人： Thien T. Nguyen , Mark I. Gardner
发明人： Thien T. Nguyen , Mark I. Gardner
IPC分类号： C23F100
CPC分类号： C23F4/00 , H01L21/32136 , H01L21/76838
摘要： Methods of fabricating interconnects of aluminum and aluminum alloys are provided. In one aspect, a method is provided for fabricating an interconnect of aluminum-containing material on a surface. A layer of aluminum-containing material is deposited on the surface. The layer of aluminum-containing material is masked with selected portions thereof left exposed. A first etch of the exposed portions is performed in a plasma ambient containing BCl3, Cl2, N2 and CF4 to establish a plurality of trenches having inwardly sloping sidewalls. An overetch of the exposed portions is performed to the surface in a plasma ambient. High aspect ratio lines may be formed with sloped sidewalls that facilitate subsequent interlevel dielectric formation.
摘要翻译：提供制造铝和铝合金互连的方法。在一个方面，提供了一种用于在表面上制造含铝材料的互连的方法。一层含铝材料沉积在表面上。含铝材料层被掩盖，其中所选择的部分露出。暴露部分的第一蚀刻在含有BCl 3，Cl 2，N 2和CF 4的等离子体环境中进行，以建立具有向内倾斜侧壁的多个沟槽。在等离子体环境中对表面进行暴露部分的过蚀刻。高纵横比线可以形成有倾斜的侧壁，其有助于随后的层间电介质形成。

9. 发明授权

US6150222A Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions 有权
标题翻译：制造具有升高的间隔物形成和自对准沟道区的高性能晶体管的方法
公开(公告)号：US6150222A
公开(公告)日：2000-11-21
申请号：US226231
申请日：1999-01-07
申请人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
发明人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/66757 , H01L29/78636
摘要： The present invention is directed to a transistor formed above a layer of a dielectric material and a method of making same. In one illustrative embodiment, the method comprises forming a first layer of dielectric material, forming a plurality of source/drain regions comprised of polysilicon above said first layer of dielectric material and between said source/drain regions, and forming a second layer of dielectric material above said first layer of dielectric material. The method further comprises forming a layer of polysilicon above the second layer of dielectric material, forming a gate dielectric above said layer of polysilicon, and forming a gate conductor above said gate dielectric. The transistor structure is comprised of a first layer of dielectric material, a plurality of source/drain regions positioned above the first layer of dielectric material, a second layer of dielectric material positioned above the first layer of dielectric material, and a layer of polysilicon positioned above the second layer of dielectric material and between said source/drain regions. The structure further comprises a gate dielectric positioned above the layer of polysilicon and a gate conductor positioned above the gate dielectric.
摘要翻译：本发明涉及一种形成在电介质材料层上方的晶体管及其制造方法。在一个说明性实施例中，该方法包括形成介电材料的第一层，在所述第一介电材料层之上和所述源极/漏极区之间形成由多晶硅构成的多个源/漏区，并形成第二介电材料层在所述第一介电材料层之上。该方法还包括在第二介电材料层之上形成多晶硅层，在所述多晶硅层上形成栅极电介质，并在所述栅极电介质上方形成栅极导体。晶体管结构包括第一介电材料层，位于第一介电材料层之上的多个源极/漏极区域，位于第一介电材料层之上的第二介电材料层和位于在第二介电材料层之上和在所述源/漏区之间。该结构还包括位于多晶硅层之上的栅极电介质和位于栅极电介质上方的栅极导体。

10. 发明授权

US06242317B1 High quality isolation structure formation 有权
标题翻译：高品质的隔离结构形成
公开(公告)号：US06242317B1
公开(公告)日：2001-06-05
申请号：US09264103
申请日：1999-03-08
申请人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
发明人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method is provided for fabricating an isolation structure, the method including forming a first dielectric layer above a structure and forming an opening in the first dielectric layer and the structure, the opening having sidewalls and a bottom. The method also includes forming a second dielectric layer within the opening on a first portion of the sidewalls and above the bottom of the opening. The method further includes forming a third dielectric layer within the opening adjacent the second dielectric layer and on a second portion of the sidewalls of the opening. The method also further includes passivating bonds in the third dielectric layer to reduce charge-trapping in the third dielectric layer, forming dielectric spacers within the opening adjacent the third dielectric layer and forming a dielectric filler within the opening adjacent the dielectric spacers and above the third dielectric layer.
摘要翻译：提供了一种用于制造隔离结构的方法，所述方法包括在结构上形成第一介电层，并在第一介电层和结构中形成开口，该开口具有侧壁和底部。该方法还包括在侧壁的第一部分和开口的底部之上的开口内形成第二电介质层。该方法还包括在邻近第二电介质层的开口内和在开口的侧壁的第二部分上形成第三电介质层。该方法还包括钝化第三电介质层中的键，以减少第三电介质层中的电荷捕获，在与第三电介质层相邻的开口内形成电介质间隔物，并在邻近电介质间隔物的开口内形成电介质填料，电介质层。

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