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1. 发明授权

US06281132B1 Device and method for etching nitride spacers formed upon an integrated circuit gate conductor 有权
标题翻译：用于蚀刻形成在集成电路栅极导体上的氮化物间隔物的装置和方法
公开(公告)号：US06281132B1
公开(公告)日：2001-08-28
申请号：US09167622
申请日：1998-10-06
申请人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
发明人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
IPC分类号： H01L213065
CPC分类号： H01L21/31116
摘要： A dry etch method is presented wherein a semiconductor substrate is introduced between a first electrode and a second electrode maintained within a reaction chamber. In this method, a main etch step is performed in which a first quantity of low frequency power is applied to the pair of electrodes from an RF power source. A first gas flow is circulated through the reaction chamber during the application of power. This first gas flow includes a first argon flow, a first oxygen flow, and a first fluorocarbon flow. Applying the first quantity of low frequency power creates a first plasma for etching a portion of a nitride layer arranged above the semiconductor substrate.
摘要翻译：提出了一种干蚀刻方法，其中将半导体衬底引入到保持在反应室内的第一电极和第二电极之间。在该方法中，执行主要蚀刻步骤，其中从RF电源向第一对电极施加第一数量的低频功率。在施加电力期间，第一气流在反应室中循环。该第一气流包括第一氩气流，第一氧气流和第一碳氟化合物流。施加第一量的低频功率产生第一等离子体，用于蚀刻布置在半导体衬底上方的氮化物层的一部分。

2. 发明授权

US6150222A Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions 有权
标题翻译：制造具有升高的间隔物形成和自对准沟道区的高性能晶体管的方法
公开(公告)号：US6150222A
公开(公告)日：2000-11-21
申请号：US226231
申请日：1999-01-07
申请人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
发明人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/66757 , H01L29/78636
摘要： The present invention is directed to a transistor formed above a layer of a dielectric material and a method of making same. In one illustrative embodiment, the method comprises forming a first layer of dielectric material, forming a plurality of source/drain regions comprised of polysilicon above said first layer of dielectric material and between said source/drain regions, and forming a second layer of dielectric material above said first layer of dielectric material. The method further comprises forming a layer of polysilicon above the second layer of dielectric material, forming a gate dielectric above said layer of polysilicon, and forming a gate conductor above said gate dielectric. The transistor structure is comprised of a first layer of dielectric material, a plurality of source/drain regions positioned above the first layer of dielectric material, a second layer of dielectric material positioned above the first layer of dielectric material, and a layer of polysilicon positioned above the second layer of dielectric material and between said source/drain regions. The structure further comprises a gate dielectric positioned above the layer of polysilicon and a gate conductor positioned above the gate dielectric.
摘要翻译：本发明涉及一种形成在电介质材料层上方的晶体管及其制造方法。在一个说明性实施例中，该方法包括形成介电材料的第一层，在所述第一介电材料层之上和所述源极/漏极区之间形成由多晶硅构成的多个源/漏区，并形成第二介电材料层在所述第一介电材料层之上。该方法还包括在第二介电材料层之上形成多晶硅层，在所述多晶硅层上形成栅极电介质，并在所述栅极电介质上方形成栅极导体。晶体管结构包括第一介电材料层，位于第一介电材料层之上的多个源极/漏极区域，位于第一介电材料层之上的第二介电材料层和位于在第二介电材料层之上和在所述源/漏区之间。该结构还包括位于多晶硅层之上的栅极电介质和位于栅极电介质上方的栅极导体。

3. 发明授权

US06242317B1 High quality isolation structure formation 有权
标题翻译：高品质的隔离结构形成
公开(公告)号：US06242317B1
公开(公告)日：2001-06-05
申请号：US09264103
申请日：1999-03-08
申请人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
发明人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method is provided for fabricating an isolation structure, the method including forming a first dielectric layer above a structure and forming an opening in the first dielectric layer and the structure, the opening having sidewalls and a bottom. The method also includes forming a second dielectric layer within the opening on a first portion of the sidewalls and above the bottom of the opening. The method further includes forming a third dielectric layer within the opening adjacent the second dielectric layer and on a second portion of the sidewalls of the opening. The method also further includes passivating bonds in the third dielectric layer to reduce charge-trapping in the third dielectric layer, forming dielectric spacers within the opening adjacent the third dielectric layer and forming a dielectric filler within the opening adjacent the dielectric spacers and above the third dielectric layer.
摘要翻译：提供了一种用于制造隔离结构的方法，所述方法包括在结构上形成第一介电层，并在第一介电层和结构中形成开口，该开口具有侧壁和底部。该方法还包括在侧壁的第一部分和开口的底部之上的开口内形成第二电介质层。该方法还包括在邻近第二电介质层的开口内和在开口的侧壁的第二部分上形成第三电介质层。该方法还包括钝化第三电介质层中的键，以减少第三电介质层中的电荷捕获，在与第三电介质层相邻的开口内形成电介质间隔物，并在邻近电介质间隔物的开口内形成电介质填料，电介质层。

4. 发明授权

US6080676A Device and method for etching spacers formed upon an integrated circuit gate conductor 有权
标题翻译：用于蚀刻形成在集成电路栅极导体上的间隔物的装置和方法
公开(公告)号：US6080676A
公开(公告)日：2000-06-27
申请号：US154843
申请日：1998-09-17
申请人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
发明人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L29/78
CPC分类号： H01L21/31116
摘要： A dry etch process is presented wherein a semiconductor substrate is introduced into a reaction chamber between a first electrode and a second electrode. The semiconductor substrate may be positioned on the first electrode. A main flow of gas that includes an argon flow at an argon flow rate and a fluorocarbon flow at a fluorocarbon flow rate is established into the reaction chamber. RF power at a low frequency may then be applied to the first electrode for creating a fluorine-deficient plasma. An oxide layer arranged above the semiconductor substrate is exposed to the fluorine-deficient plasma for etching, in a single step, a portion of the oxide layer.
摘要翻译：提出了一种干蚀刻工艺，其中半导体衬底被引入第一电极和第二电极之间的反应室中。半导体衬底可以位于第一电极上。在反应室内形成包含氩气流量的氩气流和碳氟化合物流量的碳氟化合物流的主要气流。然后可以将低频的RF功率施加到第一电极以产生缺氟等离子体。布置在半导体衬底上方的氧化物层暴露于氟缺陷等离子体，以在一个步骤中蚀刻氧化物层的一部分。

5. 发明授权

US06207544B1 Method of fabricating ultra thin nitride spacers and device incorporating same 有权
标题翻译：制造超薄氮化物间隔物的方法和结合其的装置
公开(公告)号：US06207544B1
公开(公告)日：2001-03-27
申请号：US09207808
申请日：1998-12-09
申请人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
发明人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
IPC分类号： H01L213065
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/31116 , H01L29/6656
摘要： The present invention is directed to a method of fabricating very thin silicon nitride spacers on a transistor, and to a device comprising such spacers. In one illustrative embodiment, the method comprises forming a gate dielectric above a surface of a semiconducting substrate, forming a gate conductor above the gate dielectric, and forming a layer of silicon nitride above the substrate. The method further comprises performing at least one anisotropic etching process on the layer of silicon nitride using an etching recipe comprised of helium (He), sulfur hexafluoride (SF6) and hydrogen bromide (HBr). The transistor of the present invention is comprised of a gate dielectric positioned above the surface of a semiconducting substrate and a gate conductor positioned above the gate dielectric. The transistor further comprises a plurality of source/drain regions formed in the substrate adjacent the gate dielectric and a plurality of sidewall spacers comprised of silicon nitride, each of the sidewall spacers having a thickness that ranges from approximately 200-350 Å.
摘要翻译：本发明涉及一种在晶体管上制造非常薄的氮化硅间隔物的方法以及包括这种间隔物的装置。在一个说明性实施例中，该方法包括在半导体衬底的表面上形成栅极电介质，在栅极电介质上形成栅极导体，并在衬底上方形成氮化硅层。该方法还包括使用由氦（He），六氟化硫（SF 6）和溴化氢（HBr）组成的蚀刻配方对氮化硅层进行至少一个各向异性蚀刻工艺。本发明的晶体管包括位于半导体衬底的表面上方的栅极电介质和位于栅极电介质上方的栅极导体。晶体管还包括形成在邻近栅极电介质的衬底中的多个源极/漏极区域和由氮化硅构成的多个侧壁间隔物，每个侧壁间隔物的厚度范围为约200-350埃。

6. 发明授权

US06248252B1 Method of fabricating sub-micron metal lines 有权
标题翻译：制造亚微米金属线的方法
公开(公告)号：US06248252B1
公开(公告)日：2001-06-19
申请号：US09256541
申请日：1999-02-24
申请人： Thien T. Nguyen , Mark I. Gardner
发明人： Thien T. Nguyen , Mark I. Gardner
IPC分类号： C23F100
CPC分类号： C23F4/00 , H01L21/32136 , H01L21/76838
摘要： Methods of fabricating interconnects of aluminum and aluminum alloys are provided. In one aspect, a method is provided for fabricating an interconnect of aluminum-containing material on a surface. A layer of aluminum-containing material is deposited on the surface. The layer of aluminum-containing material is masked with selected portions thereof left exposed. A first etch of the exposed portions is performed in a plasma ambient containing BCl3, Cl2, N2 and CF4 to establish a plurality of trenches having inwardly sloping sidewalls. An overetch of the exposed portions is performed to the surface in a plasma ambient. High aspect ratio lines may be formed with sloped sidewalls that facilitate subsequent interlevel dielectric formation.
摘要翻译：提供制造铝和铝合金互连的方法。在一个方面，提供了一种用于在表面上制造含铝材料的互连的方法。一层含铝材料沉积在表面上。含铝材料层被掩盖，其中所选择的部分露出。暴露部分的第一蚀刻在含有BCl 3，Cl 2，N 2和CF 4的等离子体环境中进行，以建立具有向内倾斜侧壁的多个沟槽。在等离子体环境中对表面进行暴露部分的过蚀刻。高纵横比线可以形成有倾斜的侧壁，其有助于随后的层间电介质形成。

7. 发明授权

US6162692A Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor 失效
标题翻译：扩散阻挡层和反掺杂剂区域的集成，以保持晶体管结的掺杂剂水平
公开(公告)号：US6162692A
公开(公告)日：2000-12-19
申请号：US105721
申请日：1998-06-26
申请人： Mark I. Gardner , Derrick J. Wristers , Thien T. Nguyen
发明人： Mark I. Gardner , Derrick J. Wristers , Thien T. Nguyen
IPC分类号： H01L21/265 , H01L21/336 , H01L21/425
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/66659
摘要： An integrated circuit fabrication process is provided for placing a diffusion barrier layer above the junctions of a transistor and counter dopant regions at the boundaries of the junctions to enhance the dopant level within the junctions. The diffusion barrier layer (e.g., a nitride layer) is strategically placed between the junctions and sidewall spacers which extend laterally from the opposed sidewall surfaces of a gate conductor. The diffusion barrier layer inhibits the dopants within the junctions from passing into the sidewall spacers. Dopant species opposite in type to those in the junctions are implanted into the counter dopant regions using a "large tilt angle" (LTA) implant methodology, wherein the angle of incidence of the injected dopant ions is at a non-perpendicular angle relative to the upper surface of the semiconductor substrate. In this manner, the counter dopant regions are placed both beneath the junctions and at the juncture between the junctions and the channel region of the transistor. The counter dopants fill vacancy and interstitial sites within the substrate, and thus block migration avenues through which the dopants in the junctions could otherwise pass into other areas of the substrate. The integration of the diffusion barrier layer with the counter dopant regions ensures that the dopant concentration within the junctions will be maintained.
摘要翻译：提供集成电路制造工艺，用于在结点的边界处的晶体管和反掺杂剂区域的结的上方放置扩散阻挡层，以增强接合处的掺杂剂水平。策略性地将扩散阻挡层（例如，氮化物层）放置在从栅极导体的相对的侧壁表面横向延伸的接头和侧壁间隔件之间。扩散阻挡层抑制接合处的掺杂剂进入侧壁间隔物。使用“大倾斜角”（LTA）植入方法将类型与接合点相反的掺杂物质注入到反掺杂剂区域中，其中注入的掺杂剂离子的入射角相对于半导体衬底的上表面。以这种方式，反掺杂剂区域被放置在结点之下并且在晶体管的结和沟道区之间的接合处。反掺杂剂填充衬底内的空位和间隙位置，因此阻挡迁移通道，通过该途径掺杂剂可以通过其途径进入衬底的其它区域。扩散阻挡层与反掺杂剂区域的集成确保了连接处的掺杂剂浓度将得到保持。

8. 发明授权

US6114251A Method of fabrication for ultra thin nitride liner in silicon trench isolation 失效
标题翻译：硅沟隔离中超薄氮化物衬垫的制造方法
公开(公告)号：US6114251A
公开(公告)日：2000-09-05
申请号：US226024
申请日：1999-01-06
申请人： Thien T. Nguyen , Mark I. Gardner , Frederick N. Hause
发明人： Thien T. Nguyen , Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/311 , H01L21/762 , H01L21/3065
CPC分类号： H01L21/31116 , H01L21/76224
摘要： An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in the substrate and a first insulating layer in the trench that has a bottom, a first sidewall and a second sidewall. Silicon nitride is deposited in the trench. Silicon nitride is removed from the bottom of the first insulating layer to establish a layer of silicon nitride on the first and second sidewalls by performing a first plasma etch of the deposited silicon nitride with an ambient containing He, SF.sub.6, and HBr, and a second plasma etch with an ambient containing He, SF.sub.6, and HBr. An insulating material is deposited in the trench. The method provides for reliable manufacture of nitride liners for trench isolation structures. Scaling is enhanced and the potential for parasitic leakage current due to liner oxide fracture or irregularity is reduced.
摘要翻译：提供隔离结构及其制造方法。在一个方面，该方法包括以下步骤：在衬底中形成沟槽，在沟槽中形成第一绝缘层，该第一绝缘层具有底部，第一侧壁和第二侧壁。氮化硅沉积在沟槽中。从第一绝缘层的底部去除氮化硅，以通过对包含He，SF 6和HBr的环境进行沉积的氮化硅的第一等离子体蚀刻在第一和第二侧壁上建立氮化硅层，第二用含有He，SF6和HBr的环境进行等离子体蚀刻。绝缘材料沉积在沟槽中。该方法提供可靠地制造用于沟槽隔离结构的氮化物衬垫。缩放增加，并且由于衬垫氧化物断裂或不规则性引起的寄生漏电流的可能性降低。

9. 发明授权

US6074919A Method of forming an ultrathin gate dielectric 有权
标题翻译：形成超薄栅极电介质的方法
公开(公告)号：US6074919A
公开(公告)日：2000-06-13
申请号：US234561
申请日：1999-01-20
申请人： Mark I. Gardner , Thien T. Nguyen
发明人： Mark I. Gardner , Thien T. Nguyen
IPC分类号： H01L21/28 , H01L21/336 , H01L27/06 , H01L29/417 , H01L29/49 , H01L29/51
CPC分类号： H01L29/513 , H01L21/28052 , H01L21/28194 , H01L27/0688 , H01L29/41775 , H01L29/41783 , H01L29/66583 , H01L21/28202 , H01L29/495 , H01L29/517 , H01L29/518
摘要： A method is provided for fabricating a transistor, the method including forming a semiconducting layer above a substrate layer, forming a first dielectric layer above the semiconducting layer and forming a sacrificial layer above the first dielectric layer. The method also includes forming an opening in the sacrificial layer, the first dielectric layer and the semiconducting layer to expose a channel region in the substrate layer. The method further includes forming a gate dielectric above the channel region in the substrate layer within the opening and forming a gate conductor above the gate dielectric within the opening. Moreover, the method includes removing the sacrificial layer to expose sides of the gate conductor and introducing a dopant into the semiconducting layer to form doped source/drain regions. In addition, the method includes forming dielectric spacers adjacent the gate conductor.
摘要翻译：提供了一种用于制造晶体管的方法，所述方法包括在衬底层上形成半导体层，在半导体层上形成第一介电层，并在第一介电层上方形成牺牲层。该方法还包括在牺牲层，第一介电层和半导体层中形成开口以暴露衬底层中的沟道区。该方法还包括在开口内的衬底层中的沟道区域的上方形成栅极电介质，并在开口内部的栅极电介质的上方形成栅极导体。此外，该方法包括去除牺牲层以暴露栅极导体的侧面并将掺杂剂引入到半导体层中以形成掺杂的源极/漏极区域。此外，该方法包括在栅极导体附近形成介电间隔物。

10. 发明授权

US06743688B1 High performance MOSFET with modulated channel gate thickness 失效
标题翻译：具有调制通道栅极厚度的高性能MOSFET
公开(公告)号：US06743688B1
公开(公告)日：2004-06-01
申请号：US09002964
申请日：1998-01-05
申请人： Mark I. Gardner , H. James Fulford , Charles E. May
发明人： Mark I. Gardner , H. James Fulford , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/265 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/518 , H01L29/66553 , H01L29/66583 , H01L29/78 , Y10S438/981
摘要： A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.
摘要翻译：具有第一厚度和第二厚度的栅极氧化物的半导体器件通过首先用氮离子注入半导体衬底的栅极区域的一部分，然后在栅极区域上形成栅极氧化物来形成。优选地，通过将栅极区域暴露于氧气环境来生长栅极氧化物。氮注入抑制氧气环境中的二氧化硅生长速率。因此，具有植入氮原子的栅极区域的部分将生长或形成诸如SiO 2的栅极氧化物层，其比栅极区域较少注入或未注入氮原子的部分更薄。可以沉积栅极氧化物层而不是生长栅极氧化物层。在形成栅极氧化物层之后，将多晶硅沉积到栅极氧化物上。然后可以注入半导体衬底以形成掺杂的漏极和源极区域。然后可以将间隔物放置在漏极和源极区域上并且邻近栅极的侧壁的端部。

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