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1. 发明授权

US08054871B2 Semiconductor device and semiconductor integrated circuit 有权
标题翻译：半导体器件和半导体集成电路
公开(公告)号：US08054871B2
公开(公告)日：2011-11-08
申请号：US12370338
申请日：2009-02-12
申请人： Makoto Saen , Kenichi Osada , Shigenobu Komatsu , Itaru Nonomura , Yasuhisa Shimazaki
发明人： Makoto Saen , Kenichi Osada , Shigenobu Komatsu , Itaru Nonomura , Yasuhisa Shimazaki
IPC分类号： H04L5/16 , H04B1/38
CPC分类号： H01L25/0657 , H01L24/16 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2924/14 , H01L2924/15311 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107
摘要： A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.
摘要翻译：一种半导体器件，包括能够通过无线彼此通信的一对叠层半导体IC。每个IC具有：发射机电路，其可操作来通过无线发送数据与决定发送定时的时钟信号一起发送，并且被布置成使得无线发送定时是可调节的; 接收机电路，可操作以与由无线接收的时钟信号同步地接收数据，并且被布置为使得其无线接收定时是可调节的; 以及控制电路，其可操作以基于由所述另一IC响应于通过所述发射机电路发送的数据并由所述接收机电路接收的数据的认证的结果执行所述发射机和接收机电路的定时调整。用于层叠半导体IC之间的近场通信的这种布置使得能够减少用于通信定时调整的电路的规模; 并高度准确地调整通讯时机。

2. 发明申请

US20090245445A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体器件和半导体集成电路
公开(公告)号：US20090245445A1
公开(公告)日：2009-10-01
申请号：US12370338
申请日：2009-02-12
申请人： Makoto Saen , Kenichi Osada , Shigenobu Komatsu , Itaru Nonomura , Yasuhisa Shimazaki
发明人： Makoto Saen , Kenichi Osada , Shigenobu Komatsu , Itaru Nonomura , Yasuhisa Shimazaki
IPC分类号： H04L7/00
CPC分类号： H01L25/0657 , H01L24/16 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2924/14 , H01L2924/15311 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107
摘要： A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.
摘要翻译：一种半导体器件，包括能够通过无线彼此通信的一对叠层半导体IC。每个IC具有：发射机电路，其可操作来通过无线发送数据与决定发送定时的时钟信号一起发送，并且被布置成使得无线发送定时是可调节的; 接收机电路，可操作以与由无线接收的时钟信号同步地接收数据，并且被布置为使得其无线接收定时是可调节的; 以及控制电路，其可操作以基于由所述另一IC响应于通过所述发射机电路发送的数据并由所述接收机电路接收的数据的认证的结果执行所述发射机和接收机电路的定时调整。用于层叠半导体IC之间的近场通信的这种布置使得能够减少用于通信定时调整的电路的规模; 并高度准确地调整通讯时机。

3. 发明申请

US20100177580A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：半导体集成电路器件及其工作方法
公开(公告)号：US20100177580A1
公开(公告)日：2010-07-15
申请号：US12687339
申请日：2010-01-14
申请人： Shigenobu Komatsu , Masanao Yamaoka , Noriaki Maeda , Masao Morimoto , Yasuhisa Shimazaki
发明人： Shigenobu Komatsu , Masanao Yamaoka , Noriaki Maeda , Masao Morimoto , Yasuhisa Shimazaki
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C11/413 , G11C7/08 , G11C7/22 , G11C7/227
摘要： Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.
摘要翻译：即使使用复制位线的存储器的存储器容量更高，读出放大器使能信号的产生定时的波动也减小。半导体集成电路器件包括多个字线，多个位线，多个普通存储器单元，访问控制电路，多个读出放大器，第一和第二复制位线，第一和第二复制存储单元，以及第一和第二逻辑电路。第一和第二复制存储器单元分别连接到第一和第二复制位线; 第一和第二逻辑电路的输入分别连接到第一和第二复制位线; 从第二逻辑电路的输出产生读出放大器使能信号; 并且该信号被提供给多个感测放大器。

4. 发明授权

US08125845B2 Semiconductor integrated circuit device and operating method thereof 有权
标题翻译：半导体集成电路器件及其操作方法
公开(公告)号：US08125845B2
公开(公告)日：2012-02-28
申请号：US12687339
申请日：2010-01-14
申请人： Shigenobu Komatsu , Masanao Yamaoka , Noriaki Maeda , Masao Morimoto , Yasuhisa Shimazaki
发明人： Shigenobu Komatsu , Masanao Yamaoka , Noriaki Maeda , Masao Morimoto , Yasuhisa Shimazaki
IPC分类号： G11C7/00
CPC分类号： G11C11/413 , G11C7/08 , G11C7/22 , G11C7/227
摘要： Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.
摘要翻译：即使使用复制位线的存储器的存储器容量更高，读出放大器使能信号的产生定时的波动也减小。半导体集成电路器件包括多个字线，多个位线，多个普通存储器单元，访问控制电路，多个读出放大器，第一和第二复制位线，第一和第二复制存储单元，以及第一和第二逻辑电路。第一和第二复制存储器单元分别连接到第一和第二复制位线; 第一和第二逻辑电路的输入分别连接到第一和第二复制位线; 从第二逻辑电路的输出产生读出放大器使能信号; 并且该信号被提供给多个感测放大器。

5. 发明授权

US08854869B2 Semiconductor integrated circuit device and system 有权
标题翻译：半导体集成电路器件及系统
公开(公告)号：US08854869B2
公开(公告)日：2014-10-07
申请号：US12855691
申请日：2010-08-12
申请人： Shigenobu Komatsu , Masanao Yamaoka , Noriaki Maeda , Masao Morimoto , Yasuhisa Shimazaki , Yasuyuki Okuma , Toshiaki Sano
发明人： Shigenobu Komatsu , Masanao Yamaoka , Noriaki Maeda , Masao Morimoto , Yasuhisa Shimazaki , Yasuyuki Okuma , Toshiaki Sano
IPC分类号： G11C11/00 , G11C5/14 , G11C5/06 , G11C11/413
CPC分类号： G11C11/417 , G11C5/06 , G11C5/14 , G11C11/413 , H01L27/092 , H01L27/1104
摘要： A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.
摘要翻译：提供了可以对备用时的保留数据量的变化进行响应的半导体集成电路。半导体集成电路包括逻辑电路（逻辑）和多个SRAM模块。多个SRAM模块独立于逻辑电路进行功率控制，并且在多个SRAM模块之间执行独立的功率控制。具体地，每个SRAM模块的电位控制电路的一个端子和另一个端子分别耦合到单元阵列和本地电力线。一个SRAM模块的本地电源线和另一个SRAM模块的本地电源线共享一个共享的本地电源线。一个SRAM模块的电源开关和另一个SRAM模块的电源开关共同耦合到共享的本地电源线。

6. 发明申请

US20110063895A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM 有权
标题翻译：半导体集成电路设备与系统
公开(公告)号：US20110063895A1
公开(公告)日：2011-03-17
申请号：US12855691
申请日：2010-08-12
申请人： Shigenobu KOMATSU , Masanao Yamaoka , Noriaki Maeda , Masao Morimoto , Yasuhisa Shimazaki , Yasuyuki Okuma , Toshiaki Sano
发明人： Shigenobu KOMATSU , Masanao Yamaoka , Noriaki Maeda , Masao Morimoto , Yasuhisa Shimazaki , Yasuyuki Okuma , Toshiaki Sano
IPC分类号： G11C11/417 , G11C11/412 , G11C5/14
CPC分类号： G11C11/417 , G11C5/06 , G11C5/14 , G11C11/413 , H01L27/092 , H01L27/1104
摘要： A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.
摘要翻译：提供了可以对备用时的保留数据量的变化进行响应的半导体集成电路。半导体集成电路包括逻辑电路（逻辑）和多个SRAM模块。多个SRAM模块独立于逻辑电路进行功率控制，并且在多个SRAM模块之间执行独立的功率控制。具体地，每个SRAM模块的电位控制电路的一个端子和另一个端子分别耦合到单元阵列和本地电力线。一个SRAM模块的本地电源线和另一个SRAM模块的本地电源线共享一个共享的本地电源线。一个SRAM模块的电源开关和另一个SRAM模块的电源开关共同耦合到共享的本地电源线。

7. 发明授权

US06559006B2 Semiconductor integrated circuit and method for manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06559006B2
公开(公告)日：2003-05-06
申请号：US10157978
申请日：2002-05-31
申请人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
发明人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
IPC分类号： H01L218242
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译：提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

8. 发明授权

US06436753B1 Semiconductor integrated circuit and method for manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06436753B1
公开(公告)日：2002-08-20
申请号：US09372007
申请日：1999-08-11
申请人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
发明人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
IPC分类号： H01L218244
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits, such as a microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译：提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。为了设置驱动MISFET Qd的Vth，对于形成SRAM的存储单元的负载电阻QL的转移MISFET Qt和MISFET相对有意地高于诸如微处理器的SRAM外围电路和逻辑电路的预定MISFET的Vth，引入杂质引入步骤，用于设置用于设置预定MISFET的Vth的杂质引入步骤的驱动MISFET Qd，负载电阻的转移MISFET Qt和MISFET的Vth。

9. 发明授权

US06345010B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US06345010B2
公开(公告)日：2002-02-05
申请号：US09754132
申请日：2001-01-05
申请人： Yasuhisa Shimazaki , Kenichi Osada , Hiroshi Maruyama , Naotoshi Nishioka
发明人： Yasuhisa Shimazaki , Kenichi Osada , Hiroshi Maruyama , Naotoshi Nishioka
IPC分类号： G11C800
CPC分类号： G11C7/18 , G11C11/419
摘要： A semiconductor storage device controls crosstalk of write data to read data during reading and writing operations performed in the same cycle. The device has a plurality of word lines WL, a plurality of bit lines LBL, memory cells CELL which are connected to the word lines and the bit lines, reading global bit lines RGBL connected to a sense amplifier SA and writing global bit lines WBGL connected to a write amplifier WA. A selection circuit YSWn selectively connects the reading and writing global bit lines with the local bit lines. For first and second writing global bit lines arranged between first and second reading global bit lines, a distance between the first writing global bit line and the first reading global bit line, or a distance between the second writing global bit line and the second reading global bit line being is longer than a distance between the first and second writing global bit lines. Alternatively, the writing and reading global bit lines are formed in different wiring layers in the substrate of the device.
摘要翻译：半导体存储装置控制在同一周期中执行的读写操作期间写入数据的串扰以读取数据。该器件具有多个字线WL，多个位线LBL，连接到字线和位线的存储单元CELL，读取连接到读出放大器SA的全局位线RGBL，并连接全局位线WBGL 写入放大器WA。选择电路YSWn选择性地将读写全局位线与本地位线连接。对于布置在第一和第二读取全局位线之间的第一和第二写入全局位线，第一写入全局位线和第一读取全局位线之间的距离，或者第二写入全局位线和第二读取全局位线之间的距离位线长于第一和第二写入全局位线之间的距离。或者，写入和读取全局位线形成在器件的衬底中的不同布线层中。

10. 发明授权

US06522565B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US06522565B2
公开(公告)日：2003-02-18
申请号：US10006670
申请日：2001-12-10
申请人： Yasuhisa Shimazaki , Kenichi Osada , Hiroshi Maruyama , Naotoshi Nishioka
发明人： Yasuhisa Shimazaki , Kenichi Osada , Hiroshi Maruyama , Naotoshi Nishioka
IPC分类号： G11C506
CPC分类号： G11C7/18 , G11C11/419
摘要： A semiconductor storage device controls crosstalk of write data to read data during reading and writing operations performed in the same cycle. The device has a plurality of work lines WL, a plurality of bit lines LBL, memory cells CELL which are connected to the word lines and the bit lines, reading global bit lines RGBL connected to a sense amplifier SA and writing global bit lines WBGL connected to a write amplifier WA. A selection circuit YSWn selectively connects the reading and writing global bit lines with the local bit lines. For first and second writing global bit lines arranged between first and second reading global bit lines, a distance between the first writing global bit line and the first reading global bit line, or a distance between the second writing global bit line and the second reading global bit line being is longer than a distance between the first and second writing global bit lines. Alternatively, the writing and reading global bit lines are formed in different wiring layers in the substrate of the device.
摘要翻译：半导体存储装置控制在同一周期中执行的读写操作期间写入数据的串扰以读取数据。该器件具有多个工作线WL，多个位线LBL，连接到字线和位线的存储单元CELL，读取连接到读出放大器SA的全局位线RGBL，并连接全局位线WBGL 写入放大器WA。选择电路YSWn选择性地将读写全局位线与本地位线连接。对于布置在第一和第二读取全局位线之间的第一和第二写入全局位线，第一写入全局位线和第一读取全局位线之间的距离，或者第二写入全局位线和第二读取全局位线之间的距离位线长于第一和第二写入全局位线之间的距离。或者，写入和读取全局位线形成在器件的衬底中的不同布线层中。

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