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1. 发明授权

US08054871B2 Semiconductor device and semiconductor integrated circuit 有权
标题翻译：半导体器件和半导体集成电路
公开(公告)号：US08054871B2
公开(公告)日：2011-11-08
申请号：US12370338
申请日：2009-02-12
申请人： Makoto Saen , Kenichi Osada , Shigenobu Komatsu , Itaru Nonomura , Yasuhisa Shimazaki
发明人： Makoto Saen , Kenichi Osada , Shigenobu Komatsu , Itaru Nonomura , Yasuhisa Shimazaki
IPC分类号： H04L5/16 , H04B1/38
CPC分类号： H01L25/0657 , H01L24/16 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2924/14 , H01L2924/15311 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107
摘要： A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.
摘要翻译：一种半导体器件，包括能够通过无线彼此通信的一对叠层半导体IC。每个IC具有：发射机电路，其可操作来通过无线发送数据与决定发送定时的时钟信号一起发送，并且被布置成使得无线发送定时是可调节的; 接收机电路，可操作以与由无线接收的时钟信号同步地接收数据，并且被布置为使得其无线接收定时是可调节的; 以及控制电路，其可操作以基于由所述另一IC响应于通过所述发射机电路发送的数据并由所述接收机电路接收的数据的认证的结果执行所述发射机和接收机电路的定时调整。用于层叠半导体IC之间的近场通信的这种布置使得能够减少用于通信定时调整的电路的规模; 并高度准确地调整通讯时机。

2. 发明申请

US20090245445A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体器件和半导体集成电路
公开(公告)号：US20090245445A1
公开(公告)日：2009-10-01
申请号：US12370338
申请日：2009-02-12
申请人： Makoto Saen , Kenichi Osada , Shigenobu Komatsu , Itaru Nonomura , Yasuhisa Shimazaki
发明人： Makoto Saen , Kenichi Osada , Shigenobu Komatsu , Itaru Nonomura , Yasuhisa Shimazaki
IPC分类号： H04L7/00
CPC分类号： H01L25/0657 , H01L24/16 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2924/14 , H01L2924/15311 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107
摘要： A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.
摘要翻译：一种半导体器件，包括能够通过无线彼此通信的一对叠层半导体IC。每个IC具有：发射机电路，其可操作来通过无线发送数据与决定发送定时的时钟信号一起发送，并且被布置成使得无线发送定时是可调节的; 接收机电路，可操作以与由无线接收的时钟信号同步地接收数据，并且被布置为使得其无线接收定时是可调节的; 以及控制电路，其可操作以基于由所述另一IC响应于通过所述发射机电路发送的数据并由所述接收机电路接收的数据的认证的结果执行所述发射机和接收机电路的定时调整。用于层叠半导体IC之间的近场通信的这种布置使得能够减少用于通信定时调整的电路的规模; 并高度准确地调整通讯时机。

3. 发明申请

US20090031053A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE WITH THE SAME 有权
标题翻译：半导体集成电路和具有该半导体集成电路的半导体器件
公开(公告)号：US20090031053A1
公开(公告)日：2009-01-29
申请号：US12172512
申请日：2008-07-14
申请人： Itaru Nonomura , Makoto Saen , Kenichi Osada
发明人： Itaru Nonomura , Makoto Saen , Kenichi Osada
IPC分类号： G06F13/20 , G06F13/00 , H03L7/00
CPC分类号： G06F13/4045 , H01L2924/0002 , H01L2924/00
摘要： An interconnect configuration technology of making an access from an IP mounted on a semiconductor chip to an IP mounted on another semiconductor chip by transmitting and receiving a packet transferred through an interconnect built in a semiconductor chip among the chips using the 3D coupling technology. The device according to the technology has an initiator for transmitting an access request, a target for receiving the access request and transmitting an access response, a router for relaying the access request and the access response, and a 3D coupling circuit (three-dimensional transceiver) for performing communication with the outside, wherein the 3D coupling circuit is disposed adjacent to the router.
摘要翻译：一种互连配置技术，其通过使用3D耦合技术发送和接收通过内置在半导体芯片中的互连的芯片传输的分组，从安装在半导体芯片上的IP到安装在另一半导体芯片上的IP进行访问。根据该技术的设备具有用于发送接入请求的发起者，用于接收接入请求并发送接入响应的目标，用于中继接入请求和接入响应的路由器，以及3D耦合电路（三维收发机），用于与外部进行通信，其中所述3D耦合电路邻近所述路由器设置。

4. 发明申请

US20090021974A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090021974A1
公开(公告)日：2009-01-22
申请号：US12167228
申请日：2008-07-02
申请人： Itaru NONOMURA , Kenichi Osada , Makoto Saen
发明人： Itaru NONOMURA , Kenichi Osada , Makoto Saen
IPC分类号： G11C5/06 , H01L23/49
CPC分类号： H01L25/0657 , H01L23/48 , H01L24/06 , H01L24/48 , H01L24/73 , H01L25/18 , H01L2224/0401 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/01075 , H01L2924/01082 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate.
摘要翻译：可以堆叠具有相同设计的多个芯片的半导体器件，并且消除间隔件和插入件，以改善三维耦合信息传输能力。包括三维耦合电路（三维耦合传输端子组和三维耦合接收器端子组）的第一半导体电路; 以及包括三维耦合电路和馈通电极（电源通孔和接地通孔）的第二半导体集成电路; 并且在封装衬底上堆叠包括三维耦合电路和馈通电极的第三半导体集成电路。

5. 发明授权

US07994623B2 Semiconductor device with offset stacked integrated circuits 有权
标题翻译：具有偏移堆叠集成电路的半导体器件
公开(公告)号：US07994623B2
公开(公告)日：2011-08-09
申请号：US12167228
申请日：2008-07-02
申请人： Itaru Nonomura , Kenichi Osada , Makoto Saen
发明人： Itaru Nonomura , Kenichi Osada , Makoto Saen
IPC分类号： H01L23/02 , H01L27/00
CPC分类号： H01L25/0657 , H01L23/48 , H01L24/06 , H01L24/48 , H01L24/73 , H01L25/18 , H01L2224/0401 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/01075 , H01L2924/01082 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate.
摘要翻译：可以堆叠具有相同设计的多个芯片的半导体器件，并且消除间隔件和插入件，以改善三维耦合信息传输能力。包括三维耦合电路（三维耦合传输端子组和三维耦合接收器端子组）的第一半导体电路; 以及包括三维耦合电路和馈通电极（电源通孔和接地通孔）的第二半导体集成电路; 并且在封装衬底上堆叠包括三维耦合电路和馈通电极的第三半导体集成电路。

6. 发明授权

US07849237B2 Semiconductor integrated circuit and semiconductor device with the same 有权
标题翻译：半导体集成电路和半导体器件相同
公开(公告)号：US07849237B2
公开(公告)日：2010-12-07
申请号：US12172512
申请日：2008-07-14
申请人： Itaru Nonomura , Makoto Saen , Kenichi Osada
发明人： Itaru Nonomura , Makoto Saen , Kenichi Osada
IPC分类号： G06F13/12
CPC分类号： G06F13/4045 , H01L2924/0002 , H01L2924/00
摘要： An interconnect configuration technology of making an access from an IP mounted on a semiconductor chip to an IP mounted on another semiconductor chip by transmitting and receiving a packet transferred through an interconnect built in a semiconductor chip among the chips using the 3D coupling technology. The device according to the technology has an initiator for transmitting an access request, a target for receiving the access request and transmitting an access response, a router for relaying the access request and the access response, and a 3D coupling circuit (three-dimensional transceiver) for performing communication with the outside, wherein the 3D coupling circuit is disposed adjacent to the router.
摘要翻译：一种互连配置技术，其通过使用3D耦合技术发送和接收通过内置在半导体芯片中的互连的芯片传输的分组，从安装在半导体芯片上的IP到安装在另一半导体芯片上的IP进行访问。根据该技术的设备具有用于发送接入请求的发起者，用于接收接入请求并发送接入响应的目标，用于中继接入请求和接入响应的路由器，以及3D耦合电路（三维收发机），用于与外部进行通信，其中所述3D耦合电路邻近所述路由器设置。

7. 发明申请

US20100117697A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD FOR CLOCK SIGNAL SYNCHRONIZATION 失效
标题翻译：用于时钟信号同步的半导体集成电路和控制方法
公开(公告)号：US20100117697A1
公开(公告)日：2010-05-13
申请号：US12615607
申请日：2009-11-10
申请人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
发明人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F1/10 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03L7/0818 , H03L7/089 , Y02D10/126 , Y02D10/172
摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
摘要翻译：在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。第一电路（FVA）使用第一电源电压（VDDA）进行操作。第二电路（NFVA）使用第二电源电压（VDDB）进行操作。可以在将时钟发送到这些电路的路径之间调整时钟延迟。当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。

8. 发明授权

US08350595B2 Semiconductor integrated circuit and control method for clock signal synchronization 失效
标题翻译：半导体集成电路和时钟信号同步控制方法
公开(公告)号：US08350595B2
公开(公告)日：2013-01-08
申请号：US13438050
申请日：2012-04-03
申请人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
发明人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
IPC分类号： G01R25/00 , H03D13/00
CPC分类号： H03L7/0814 , G06F1/10 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03L7/0818 , H03L7/089 , Y02D10/126 , Y02D10/172
摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
摘要翻译：在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。第一电路（FVA）使用第一电源电压（VDDA）进行操作。第二电路（NFVA）使用第二电源电压（VDDB）进行操作。可以在将时钟发送到这些电路的路径之间调整时钟延迟。当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。

9. 发明申请

US20120187993A1 Semiconductor Integrated Circuit and Control Method for Clock Signal Synchronization 失效
标题翻译：半导体集成电路和时钟信号同步控制方法
公开(公告)号：US20120187993A1
公开(公告)日：2012-07-26
申请号：US13438050
申请日：2012-04-03
申请人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
发明人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F1/10 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03L7/0818 , H03L7/089 , Y02D10/126 , Y02D10/172
摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
摘要翻译：在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。第一电路（FVA）使用第一电源电压（VDDA）进行操作。第二电路（NFVA）使用第二电源电压（VDDB）进行操作。可以在将时钟发送到这些电路的路径之间调整时钟延迟。当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。

10. 发明授权

US08183899B2 Semiconductor integrated circuit and control method for clock signal synchronization 失效
标题翻译：半导体集成电路和时钟信号同步控制方法
公开(公告)号：US08183899B2
公开(公告)日：2012-05-22
申请号：US12615607
申请日：2009-11-10
申请人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
发明人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , G06F1/10 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03L7/0818 , H03L7/089 , Y02D10/126 , Y02D10/172
摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
摘要翻译：在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。第一电路（FVA）使用第一电源电压（VDDA）进行操作。第二电路（NFVA）使用第二电源电压（VDDB）进行操作。可以在将时钟发送到这些电路的路径之间调整时钟延迟。当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。

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