专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090021974A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090021974A1
公开(公告)日：2009-01-22
申请号：US12167228
申请日：2008-07-02
申请人： Itaru NONOMURA , Kenichi Osada , Makoto Saen
发明人： Itaru NONOMURA , Kenichi Osada , Makoto Saen
IPC分类号： G11C5/06 , H01L23/49
CPC分类号： H01L25/0657 , H01L23/48 , H01L24/06 , H01L24/48 , H01L24/73 , H01L25/18 , H01L2224/0401 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/01075 , H01L2924/01082 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate.
摘要翻译：可以堆叠具有相同设计的多个芯片的半导体器件，并且消除间隔件和插入件，以改善三维耦合信息传输能力。包括三维耦合电路（三维耦合传输端子组和三维耦合接收器端子组）的第一半导体电路; 以及包括三维耦合电路和馈通电极（电源通孔和接地通孔）的第二半导体集成电路; 并且在封装衬底上堆叠包括三维耦合电路和馈通电极的第三半导体集成电路。

2. 发明申请

US20090059943A1 DATA PROCESSING SYSTEM 审中-公开
标题翻译：数据处理系统
公开(公告)号：US20090059943A1
公开(公告)日：2009-03-05
申请号：US12193000
申请日：2008-08-16
申请人： Itaru NONOMURA
发明人： Itaru NONOMURA
IPC分类号： H04L12/56
CPC分类号： G06F13/4045 , Y02D10/14 , Y02D10/151
摘要： A data processing system enabling an outstanding-based variable flow control is provided. The data processing system includes a first semiconductor integrated circuit possessing an initiator and a second semiconductor integrated circuit possessing a target. The initiator transmits a request packet to the target, the target transmits a response packet to the initiator, and split transaction interface is practiced. The initiator includes an outstanding number counting circuit for counting an outstanding number defined by the difference in number between the request packets transmitted and the response packets received. The request packet transmission number is controlled so that the count value of the outstanding number counting circuit may not exceed the outstanding number to which the target can respond. The outstanding number is dynamically changeable to a suitable number so that the maximum latency from the issue of the request packet to the reception of the response packet is suppressed.
摘要翻译：提供了能够实现基于突出的可变流量控制的数据处理系统。数据处理系统包括具有启动器的第一半导体集成电路和具有目标的第二半导体集成电路。发起者向目标发送请求分组，目标向发起者发送响应分组，实现分组事务接口。启动器包括一个未完成的号码计数电路，用于对发送的请求分组和所接收的响应分组之间的数量差异定义的未完成号码进行计数。控制请求分组发送次数，使得未完成号码计数电路的计数值不能超过目标可以响应的未决号码。未完成的号码可动态地改变为合适的号码，从而抑制从发出请求分组到接收响应分组的最大等待时间。

3. 发明申请

US20110314323A1 SEMICONDUCTOR DEVICE AND DATA PROCESSOR 有权
标题翻译：半导体器件和数据处理器
公开(公告)号：US20110314323A1
公开(公告)日：2011-12-22
申请号：US13220747
申请日：2011-08-30
申请人： Yoshihiko HOTTA , Seiichi SAITO , Hiroyuki HAMASAKI , Hirotaka HARA , Itaru NONOMURA
发明人： Yoshihiko HOTTA , Seiichi SAITO , Hiroyuki HAMASAKI , Hirotaka HARA , Itaru NONOMURA
IPC分类号： G06F1/12
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译：提高从高速电路块访问低速电路块的速度，而不会显着增加功耗。在具有总线控制器的数据处理器中，总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，提供定时控制电路在外围电路和总线控制器之间，并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器速度时钟信号，使定时控制电路响应于指向外围电路的写指令而启动，与高速时钟信号的周期同步地写入外围电路，并且与低速时钟信号的周期。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式