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1. 发明申请

US20080169510A1 PERFORMANCE ENHANCEMENT ON BOTH NMOSFET AND PMOSFET USING SELF-ALIGNED DUAL STRESSED FILMS 审中-公开
标题翻译：使用自对准双应力膜的两个NMOSFET和PMOSFET的性能增强
公开(公告)号：US20080169510A1
公开(公告)日：2008-07-17
申请号：US11623871
申请日：2007-01-17
申请人： Mahender Kumar , Huilong Zhu
发明人： Mahender Kumar , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823412 , H01L27/088 , H01L27/092 , H01L29/7843
摘要： In an integrated circuit comprising both PMOSFETs and NMOSFETs, carrier mobility is enhanced on both types of FETs using dual stressed films. The adverse impact of having both layers of stressed films along the boundary between different types of films is eliminated by utilizing self-alignment of the edges of a second stressed film to a preexisting edge of a first stressed film. At the boundary between the two stressed films, one stressed film abuts another but no stressed film overlies another stressed film. By avoiding any overlap of stressed films, the stress exerted on the MOSFET channels is maximized.
摘要翻译：在包括PMOSFET和NMOSFET的集成电路中，使用双应力膜的两种类型的FET都增加了载流子迁移率。通过利用第二应力膜的边缘对第一应力膜的预先存在的边缘进行自对准，消除了沿不同类型的膜之间的边界具有两层应力膜的不利影响。在两个应力薄膜之间的边界处，一个应力薄膜邻接另一个，但没有应力薄膜覆盖另一个应力薄膜。通过避免应力膜的任何重叠，施加在MOSFET通道上的应力最大化。

2. 发明授权

US08053838B2 Structures, fabrication methods, design structures for strained fin field effect transistors (FinFets) 有权
标题翻译：应变鳍场效应晶体管的结构，制造方法，设计结构（FinFets）
公开(公告)号：US08053838B2
公开(公告)日：2011-11-08
申请号：US12146728
申请日：2008-06-26
申请人： Xiaomeng Chen , Byeong Yeol Kim , Mahender Kumar , Huilong Zhu
发明人： Xiaomeng Chen , Byeong Yeol Kim , Mahender Kumar , Huilong Zhu
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L29/7848 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain creating fin region. The first semiconductor seed region is sandwiched between the first strain creating fin region and the dielectric layer. The first semiconductor seed region includes a first semiconductor material. The first strain creating fin region includes the first semiconductor material and a second semiconductor material different than the first semiconductor material. A first atom percent of the first semiconductor material in the first semiconductor seed region is different than a second atom percent of the first semiconductor material in the first strain creating fin region.
摘要翻译： FinFet的半导体结构，制造方法和设计结构。 FinFet包括电介质层，电介质层上的中央半导体鳍片区域，电介质层上的第一半导体种子区域和第一应变产生鳍片区域。第一半导体种子区域夹在第一应变产生鳍区域和电介质层之间。第一半导体种子区域包括第一半导体材料。第一应变产生鳍区域包括第一半导体材料和与第一半导体材料不同的第二半导体材料。第一半导体晶种区域中的第一半导体材料的第一原子百分比不同于第一应变产生鳍区域中的第一半导体材料的第二原子百分比。

3. 发明申请

US20080079037A1 FIELD EFFECT DEVICE INCLUDING INVERTED V SHAPED CHANNEL REGION AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：包括反相V形通道区域的场效应装置及其制造方法
公开(公告)号：US20080079037A1
公开(公告)日：2008-04-03
申请号：US11538174
申请日：2006-10-03
申请人： Huilong Zhu , Ravikumar Ramachandran , Effendi Leobandung , Mahender Kumar , Wenjuan Zhu , Christine Norris
发明人： Huilong Zhu , Ravikumar Ramachandran , Effendi Leobandung , Mahender Kumar , Wenjuan Zhu , Christine Norris
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/78648
摘要： A semiconductor structure includes a semiconductor layer that includes an inverted V shaped channel region that allows avoidance of a raised source/drain region within the semiconductor structure. In one embodiment, a generally conventional gate electrode is located over a planar surface of the semiconductor layer over the inverted V shaped channel region. In another embodiment, the foregoing generally conventional gate electrode is used in conjunction with an inverted V shaped gate electrode that is located within an inverted V shaped notch that comprises the inverted V shaped channel region.
摘要翻译：半导体结构包括半导体层，其包括反向V形沟道区域，其允许避免半导体结构内的升高的源极/漏极区域。在一个实施例中，通常常规的栅电极位于反向V形沟道区上的半导体层的平面表面上方。在另一个实施例中，上述通常的常规栅极电极与位于包括反向V形沟道区域的倒V形凹口内的反向V形栅电极结合使用。

4. 发明授权

US07485510B2 Field effect device including inverted V shaped channel region and method for fabrication thereof 有权
标题翻译：包括倒V形沟道区域的场效应器件及其制造方法
公开(公告)号：US07485510B2
公开(公告)日：2009-02-03
申请号：US11538174
申请日：2006-10-03
申请人： Huilong Zhu , Ravikumar Ramachandran , Effendi Leobandung , Mahender Kumar , Wenjuan Zhu , Christine Norris
发明人： Huilong Zhu , Ravikumar Ramachandran , Effendi Leobandung , Mahender Kumar , Wenjuan Zhu , Christine Norris
IPC分类号： H01L21/84
CPC分类号： H01L29/78696 , H01L29/78648
摘要： A semiconductor structure includes a semiconductor layer that includes an inverted V shaped channel region that allows avoidance of a raised source/drain region within the semiconductor structure. In one embodiment, a generally conventional gate electrode is located over a planar surface of the semiconductor layer over the inverted V shaped channel region. In another embodiment, the foregoing generally conventional gate electrode is used in conjunction with an inverted V shaped gate electrode that is located within an inverted V shaped notch that comprises the inverted V shaped channel region.
摘要翻译：半导体结构包括半导体层，其包括反向V形沟道区域，其允许避免半导体结构内的升高的源极/漏极区域。在一个实施例中，通常常规的栅电极位于反向V形沟道区上的半导体层的平面表面上方。在另一个实施例中，上述通常的常规栅极电极与位于包括反向V形沟道区域的倒V形凹口内的反向V形栅电极结合使用。

5. 发明授权

US07790553B2 Methods for forming high performance gates and structures thereof 失效
标题翻译：形成高性能栅极的方法及其结构
公开(公告)号：US07790553B2
公开(公告)日：2010-09-07
申请号：US12170687
申请日：2008-07-10
申请人： Huilong Zhu , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
发明人： Huilong Zhu , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82385 , H01L21/823857
摘要： Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.
摘要翻译：公开了在MOSFET中形成高性能栅极的方法及其结构。一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET，第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。

6. 发明申请

US20090321828A1 STRUCTURES, FABRICATION METHODS, DESIGN STRUCTURES FOR STRAINED FIN FIELD EFFECT TRANSISTORS (FINFETS) 有权
标题翻译：结构，制造方法，应变金属场效应晶体管的设计结构（FINFETS）
公开(公告)号：US20090321828A1
公开(公告)日：2009-12-31
申请号：US12146728
申请日：2008-06-26
申请人： Xiaomeng Chen , Byeong Yeol Kim , Mahender Kumar , Huilong Zhu
发明人： Xiaomeng Chen , Byeong Yeol Kim , Mahender Kumar , Huilong Zhu
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L29/7848 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain creating fin region. The first semiconductor seed region is sandwiched between the first strain creating fin region and the dielectric layer. The first semiconductor seed region includes a first semiconductor material. The first strain creating fin region includes the first semiconductor material and a second semiconductor material different than the first semiconductor material. A first atom percent of the first semiconductor material in the first semiconductor seed region is different than a second atom percent of the first semiconductor material in the first strain creating fin region.
摘要翻译： FinFet的半导体结构，制造方法和设计结构。 FinFet包括电介质层，电介质层上的中央半导体鳍片区域，电介质层上的第一半导体种子区域和第一应变产生鳍片区域。第一半导体种子区域夹在第一应变产生鳍区域和电介质层之间。第一半导体种子区域包括第一半导体材料。第一应变产生鳍区域包括第一半导体材料和与第一半导体材料不同的第二半导体材料。第一半导体晶种区域中的第一半导体材料的第一原子百分比不同于第一应变产生鳍区域中的第一半导体材料的第二原子百分比。

7. 发明授权

US07528027B1 Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel 失效
标题翻译：用于在V形通道的尖端处制造具有超薄SOI的器件的结构和方法
公开(公告)号：US07528027B1
公开(公告)日：2009-05-05
申请号：US12054727
申请日：2008-03-25
申请人： Huilong Zhu , Mahender Kumar , Dan M. Mocuta , Ravikumar Ramachandran , Wenjuan Zhu
发明人： Huilong Zhu , Mahender Kumar , Dan M. Mocuta , Ravikumar Ramachandran , Wenjuan Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/82385 , H01L21/84 , H01L29/045 , H01L29/1037 , H01L29/66545 , H01L29/66621 , H01L29/66772
摘要： An SOI CMOS structure includes a v-shape trench in a pFet region. The v-shape trench has a surface in a (111) plane and extends into an SOI layer in the pFet region. A layer, such as a gate oxide or high-k material, is formed in the v-shape trench. Poly-Si is deposited on top of the layer.
摘要翻译： SOI CMOS结构包括pFet区域中的v形沟槽。 V形沟槽具有（111）面中的表面并延伸到pFet区域中的SOI层。在V形沟槽中形成诸如栅极氧化物或高k材料的层。多晶硅沉积在层的顶部。

8. 发明申请

US20090072400A1 CONTACT FORMING IN TWO PORTIONS AND CONTACT SO FORMED 审中-公开
标题翻译：联系在两个部分形成并联系形成
公开(公告)号：US20090072400A1
公开(公告)日：2009-03-19
申请号：US11856839
申请日：2007-09-18
申请人： Huilong Zhu , James J. Heaps-Nelson , Mahender Kumar , Christine Norris , Ravikumar Ramachandran
发明人： Huilong Zhu , James J. Heaps-Nelson , Mahender Kumar , Christine Norris , Ravikumar Ramachandran
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L23/485 , H01L21/76816 , H01L21/76829 , H01L21/76831 , H01L21/76847 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a contact in two or more portions and a contact so formed are disclosed. One method includes providing a device including a silicide region; and forming a contact to the silicide region by: first forming a lower contact portion to the silicide region through a first dielectric layer, and second forming an upper contact portion to the lower contact portion through a second dielectric layer over the first dielectric layer. A contact may include a first contact portion contacting a silicide region, the first contact portion having a width less than 100 nm; and a second contact portion coupled to the first contact portion from above, the second contact portion having a width greater than the width of the first contact portion.
摘要翻译：公开了在两个或多个部分形成接触的方法和如此形成的接触。一种方法包括提供包括硅化物区域的器件; 以及通过以下步骤形成与所述硅化物区的接触：首先通过第一介电层形成到所述硅化物区的下接触部分，以及通过所述第一电介质层上的第二电介质层，在所述下接触部分形成上接触部分。接触可以包括接触硅化物区域的第一接触部分，第一接触部分具有小于100nm的宽度; 以及从上方联接到所述第一接触部分的第二接触部分，所述第二接触部分的宽度大于所述第一接触部分的宽度。

9. 发明申请

US20100006926A1 METHODS FOR FORMING HIGH PERFORMANCE GATES AND STRUCTURES THEREOF 失效
标题翻译：形成高性能门和其结构的方法
公开(公告)号：US20100006926A1
公开(公告)日：2010-01-14
申请号：US12170687
申请日：2008-07-10
申请人： HUILONG ZHU , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
发明人： HUILONG ZHU , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82385 , H01L21/823857
摘要： Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.
摘要翻译：公开了在MOSFET中形成高性能栅极的方法及其结构。一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET，第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。

10. 发明授权

US07943474B2 EDRAM including metal plates 有权
标题翻译： EDRAM包括金属板
公开(公告)号：US07943474B2
公开(公告)日：2011-05-17
申请号：US12391631
申请日：2009-02-24
申请人： Thomas W. Dyer , Keith Kwong Hon Wong , Mahender Kumar
发明人： Thomas W. Dyer , Keith Kwong Hon Wong , Mahender Kumar
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L28/91
摘要： A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode.An upper electrode is then formed on the conformal dielectric layer. The forming of the upper electrode may include a conformal deposition of metal nitride layer, and a non-conformal deposition of an electrically conductive material atop the metal nitride layer, in which the electrically conductive material encloses the at least one trench.
摘要翻译：通过首先在半导体衬底中形成至少一个沟槽来提供形成存储器件的方法。接下来，在至少一个沟槽中形成下电极，之后在下电极上形成保形电介质层。然后在保形电介质层上形成上电极。上电极的形成可以包括金属氮化物层的共形沉积，以及金属氮化物层顶部的导电材料的非共形沉积，其中导电材料包围至少一个沟槽。

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