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1. 发明授权

US07943474B2 EDRAM including metal plates 有权
标题翻译： EDRAM包括金属板
公开(公告)号：US07943474B2
公开(公告)日：2011-05-17
申请号：US12391631
申请日：2009-02-24
申请人： Thomas W. Dyer , Keith Kwong Hon Wong , Mahender Kumar
发明人： Thomas W. Dyer , Keith Kwong Hon Wong , Mahender Kumar
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L28/91
摘要： A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode.An upper electrode is then formed on the conformal dielectric layer. The forming of the upper electrode may include a conformal deposition of metal nitride layer, and a non-conformal deposition of an electrically conductive material atop the metal nitride layer, in which the electrically conductive material encloses the at least one trench.
摘要翻译：通过首先在半导体衬底中形成至少一个沟槽来提供形成存储器件的方法。接下来，在至少一个沟槽中形成下电极，之后在下电极上形成保形电介质层。然后在保形电介质层上形成上电极。上电极的形成可以包括金属氮化物层的共形沉积，以及金属氮化物层顶部的导电材料的非共形沉积，其中导电材料包围至少一个沟槽。

2. 发明申请

US20100213571A1 EDRAM INCLUDING METAL PLATES 有权
标题翻译： EDRAM包括金属板
公开(公告)号：US20100213571A1
公开(公告)日：2010-08-26
申请号：US12391631
申请日：2009-02-24
申请人： Thomas W. Dyer , Keith Kwong Hon Wong , Mahender Kumar
发明人： Thomas W. Dyer , Keith Kwong Hon Wong , Mahender Kumar
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L29/66181 , H01L28/91
摘要： A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode.An upper electrode is then formed on the conformal dielectric layer. The forming of the upper electrode may include a conformal deposition of metal nitride layer, and a non-conformal deposition of an electrically conductive material atop the metal nitride layer, in which the electrically conductive material encloses the at least one trench.
摘要翻译：通过首先在半导体衬底中形成至少一个沟槽来提供形成存储器件的方法。接下来，在至少一个沟槽中形成下电极，之后在下电极上形成保形电介质层。然后在保形电介质层上形成上电极。上电极的形成可以包括金属氮化物层的共形沉积，以及金属氮化物层顶部的导电材料的非共形沉积，其中导电材料包围至少一个沟槽。

3. 发明授权

US07808082B2 Structure and method for dual surface orientations for CMOS transistors 失效
标题翻译：用于CMOS晶体管的双面取向的结构和方法
公开(公告)号：US07808082B2
公开(公告)日：2010-10-05
申请号：US11559571
申请日：2006-11-14
申请人： Haining Yang , Thomas W. Dyer , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Haining Yang , Thomas W. Dyer , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/335
CPC分类号： H01L21/30608 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/02639 , H01L21/823821 , H01L27/11 , H01L27/1104 , H01L29/7853
摘要： The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that preferentially etches a set of crystallographic planes faster than others, new facets with different surface orientations than the substrate orientation are formed on the semiconductor substrate. Alternatively, selective epitaxy may be utilized to generate new facets. The facets thus formed are joined to form a lambda shaped profile in a cross-section. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a lambda shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.
摘要翻译：本发明提供了提供具有不同于半导体衬底通常提供的不同晶体取向的刻面的结构和方法。通过掩蔽半导体表面的一部分并将其余部分暴露于比其它晶体学优化蚀刻一组结晶平面的各向异性蚀刻工艺，在半导体衬底上形成具有不同于衬底取向的不同表面取向的新面。或者，可以利用选择性外延生成新的面。如此形成的小面被连接以在横截面中形成λ形轮廓。新面的电特性，特别是增强的载流子迁移率被用于增强晶体管的性能。在具有接合形成λ形轮廓的小平面上的通道的晶体管中，电流沿连接小面的脊的方向流动，避免了在电流方向上的任何拐点。

4. 发明申请

US20080111162A1 STRUCTURE AND METHOD FOR DUAL SURFACE ORIENTATIONS FOR CMOS TRANSISTORS 失效
标题翻译： CMOS晶体管双面指向的结构与方法
公开(公告)号：US20080111162A1
公开(公告)日：2008-05-15
申请号：US11559571
申请日：2006-11-14
申请人： Haining Yang , Thomas W. Dyer , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Haining Yang , Thomas W. Dyer , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/04 , H01L21/311
CPC分类号： H01L21/30608 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/02639 , H01L21/823821 , H01L27/11 , H01L27/1104 , H01L29/7853
摘要： The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that preferentially etches a set of crystallographic planes faster than others, new facets with different surface orientations than the substrate orientation are formed on the semiconductor substrate. Alternatively, selective epitaxy may be utilized to generate new facets. The facets thus formed are joined to form a lambda shaped profile in a cross-section. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a lambda shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.
摘要翻译：本发明提供了提供具有不同于半导体衬底通常提供的不同晶体取向的刻面的结构和方法。通过掩蔽半导体表面的一部分并将其余部分暴露于比其它晶体学优化蚀刻一组结晶平面的各向异性蚀刻工艺，在半导体衬底上形成具有不同于衬底取向的不同表面取向的新面。或者，可以利用选择性外延生成新的面。如此形成的小面被连接以在横截面中形成λ形轮廓。新面的电特性，特别是增强的载流子迁移率被用于增强晶体管的性能。在具有接合形成λ形轮廓的小平面上的通道的晶体管中，电流沿连接小面的脊的方向流动，避免了在电流方向上的任何拐点。

5. 发明申请

US20130001660A1 PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 失效
公开(公告)号：US20130001660A1
公开(公告)日：2013-01-03
申请号：US13615955
申请日：2012-09-14
申请人： Thomas W. Dyer
发明人： Thomas W. Dyer
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L21/30608 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/7848
摘要： Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

6. 发明授权

US08063449B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08063449B2
公开(公告)日：2011-11-22
申请号：US12626496
申请日：2009-11-25
申请人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
发明人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
IPC分类号： H01L29/78
CPC分类号： H01L29/6656 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/165 , H01L29/41775 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。在衬套上形成填充材料。填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

7. 发明授权

US07989357B2 Method of patterning semiconductor structure and structure thereof 有权
标题翻译：图案化半导体结构及其结构的方法
公开(公告)号：US07989357B2
公开(公告)日：2011-08-02
申请号：US11950741
申请日：2007-12-05
申请人： Thomas W. Dyer , James J. Toomey
发明人： Thomas W. Dyer , James J. Toomey
IPC分类号： H01L23/48
CPC分类号： H01L21/8258 , H01L21/0337 , H01L21/28123 , H01L21/31144
摘要： Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.
摘要翻译：公开了图案化半导体结构的方法。该方法涉及晶体蚀刻技术以增强作为硬掩模的图案化单晶层。在一个实施例中，该方法包括将单晶硅层结合到非结晶保护层; 图案化单晶层以形成硬掩模; 增强硬面膜的图案; 常规蚀刻保护层后剥去硬掩模; 并在其上形成栅极氧化物。通过结晶蚀刻来进行硬掩模的增强图案化，以取代在具有直边和锐角的限定区域的端部处的圆化和尺寸变窄的光学效应。使用增强型图案化硬掩模的结果包括在半导体结构的衬底上的复合材料层。复合材料层包括在层内由直边限定的离散块中的不同材料。

8. 发明授权

US07964910B2 Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure 有权
标题翻译：平面场效应晶体管结构具有倾斜的结晶刻蚀源极/漏极凹槽和形成晶体管结构的方法
公开(公告)号：US07964910B2
公开(公告)日：2011-06-21
申请号：US11873731
申请日：2007-10-17
申请人： Thomas W. Dyer
发明人： Thomas W. Dyer
IPC分类号： H01L29/66
CPC分类号： H01L29/6656 , H01L21/30608 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/7848
摘要： Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.
摘要翻译：公开了一种结合外延沉积的源/漏半导体膜的晶体管和用于形成晶体管的方法。晶体蚀刻用于在硅衬底中的沟道区和沟槽隔离区之间形成凹陷。每个凹部具有与沟道区相邻的第一轮廓和具有与沟槽隔离区相邻的第二轮廓的第一侧。晶体蚀刻确保第二轮廓成角度，使得所有暴露的凹部表面都包含硅。因此，可以通过外延沉积而不形成凹坑来填充凹部。可以使用附加的工艺步骤来确保凹部的第一侧形成有增强通道区域中的期望应力的不同轮廓。

9. 发明授权

US07863646B2 Dual oxide stress liner 有权
标题翻译：双重氧化应力衬垫
公开(公告)号：US07863646B2
公开(公告)日：2011-01-04
申请号：US11956043
申请日：2007-12-13
申请人： Michael P. Belyansky , Xiangdong Chen , Thomas W. Dyer , Geng Wang , Haining S. Yang
发明人： Michael P. Belyansky , Xiangdong Chen , Thomas W. Dyer , Geng Wang , Haining S. Yang
IPC分类号： H01L31/111 , H01L21/00
CPC分类号： H01L21/823807 , H01L27/092 , H01L29/7843
摘要： A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor.
摘要翻译：晶体管结构包括位于衬底的第一区域中的第一类型的晶体管（例如，P型）和位于衬底的第二区域中的第二类型的晶体管（例如N型）。第一类型的应力层（压缩共形氮化物）位于第一类型的晶体管上方，并且第二类型的应力层（压缩拉伸氮化物）位于第二类型晶体管之上。此外，另一种第一类型的应力层（压缩氧化物）位于第一类型的晶体管之上。此外，另一第二类型的应力层（压缩氧化物）位于第二类型晶体管的上方。

10. 发明授权

US07749903B2 Gate patterning scheme with self aligned independent gate etch 失效
标题翻译：具有自对准独立栅极蚀刻的栅极图案化方案
公开(公告)号：US07749903B2
公开(公告)日：2010-07-06
申请号：US12027444
申请日：2008-02-07
申请人： Scott D. Halle , Matthew E. Colburn , Bruce B. Doris , Thomas W. Dyer
发明人： Scott D. Halle , Matthew E. Colburn , Bruce B. Doris , Thomas W. Dyer
IPC分类号： H01L21/44
CPC分类号： H01L21/32139 , H01L21/266 , H01L21/28123 , H01L21/823828
摘要： A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.
摘要翻译：公开了一种用于自对准栅极图案化的方法。使用两个掩模来处理相邻的半导体部件，例如由浅沟槽隔离区分隔的nFET和pFET。选择掩模材料以便于选择性蚀刻。当第一掩模仍然存在时，施加第二掩模，从而使第二掩模与第一掩模自对准。这避免了在浅沟槽隔离区域上不期望地形成纵梁，从而提高半导体制造操作的产量。

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