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1. 发明申请

US20100006926A1 METHODS FOR FORMING HIGH PERFORMANCE GATES AND STRUCTURES THEREOF 失效
标题翻译：形成高性能门和其结构的方法
公开(公告)号：US20100006926A1
公开(公告)日：2010-01-14
申请号：US12170687
申请日：2008-07-10
申请人： HUILONG ZHU , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
发明人： HUILONG ZHU , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82385 , H01L21/823857
摘要： Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.
摘要翻译：公开了在MOSFET中形成高性能栅极的方法及其结构。一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET，第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。

2. 发明授权

US07790553B2 Methods for forming high performance gates and structures thereof 失效
标题翻译：形成高性能栅极的方法及其结构
公开(公告)号：US07790553B2
公开(公告)日：2010-09-07
申请号：US12170687
申请日：2008-07-10
申请人： Huilong Zhu , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
发明人： Huilong Zhu , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82385 , H01L21/823857
摘要： Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.
摘要翻译：公开了在MOSFET中形成高性能栅极的方法及其结构。一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET，第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。

3. 发明申请

US20090079026A1 STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES 有权
标题翻译：半导体绝缘体器件的应力发生结构
公开(公告)号：US20090079026A1
公开(公告)日：2009-03-26
申请号：US11860851
申请日：2007-09-25
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

4. 发明申请

US20120139081A1 STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES 有权
标题翻译：半导体绝缘体器件的应力发生结构
公开(公告)号：US20120139081A1
公开(公告)日：2012-06-07
申请号：US13370898
申请日：2012-02-10
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

5. 发明授权

US08115254B2 Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same 有权
标题翻译：绝缘体上半导体结构，包括含有绝缘体应力插头的沟槽及其制造方法
公开(公告)号：US08115254B2
公开(公告)日：2012-02-14
申请号：US11860851
申请日：2007-09-25
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L27/12
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

6. 发明授权

US08629501B2 Stress-generating structure for semiconductor-on-insulator devices 有权
标题翻译：绝缘体上半导体器件的应力产生结构
公开(公告)号：US08629501B2
公开(公告)日：2014-01-14
申请号：US13370898
申请日：2012-02-10
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L27/12
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

7. 发明授权

US07659157B2 Dual metal gate finFETs with single or dual high-K gate dielectric 有权
标题翻译：具有单或双高K栅极电介质的双金属栅极finFET
公开(公告)号：US07659157B2
公开(公告)日：2010-02-09
申请号：US11860840
申请日：2007-09-25
申请人： Brian J. Greene , Mahender Kumar
发明人： Brian J. Greene , Mahender Kumar
IPC分类号： H01L21/8238 , H01L21/8222
CPC分类号： H01L27/1211 , H01L21/823807 , H01L21/823821 , H01L21/823842 , H01L21/845 , H01L29/66795 , H01L29/7851
摘要： A first high-k gate dielectric layer and a first metal gate layer are formed on first and second semiconductor fins. A first metal gate ring is formed on the first semiconductor fin. In one embodiment, the first high-k gate dielectric layer remains on the second semiconductor fin. A second metal gate layer and a silicon containing layer are deposited and patterned to form gate electrodes. In another embodiment, a second high-k dielectric layer replaces the first high-k dielectric layer over the second semiconductor fin, followed by formation of a second metal gate layer. A first electrode comprising a first gate dielectric and a first metal gate is formed on the first semiconductor fin, while a second electrode comprising a second gate dielectric and a second metal gate is formed on the second semiconductor fin. Absence of high-k gate dielectric materials on a gate wiring prevents increase in parasitic resistance.
摘要翻译：在第一和第二半导体鳍片上形成第一高k栅介质层和第一金属栅极层。第一金属栅环形成在第一半导体鳍上。在一个实施例中，第一高k栅介质层保留在第二半导体鳍片上。沉积第二金属栅极层和含硅层以形成栅电极。在另一个实施例中，第二高k电介质层替代第二半导体鳍片上的第一高k电介质层，随后形成第二金属栅极层。包括第一栅极电介质和第一金属栅极的第一电极形成在第一半导体鳍片上，而在第二半导体鳍片上形成包括第二栅极电介质和第二金属栅极的第二电极。在栅极布线上缺少高k栅极电介质材料可防止寄生电阻的增加。

8. 发明申请

US20090078997A1 DUAL METAL GATE FINFETS WITH SINGLE OR DUAL HIGH-K GATE DIELECTRIC 有权
标题翻译：具有单或双高K栅介质的双金属栅极熔体
公开(公告)号：US20090078997A1
公开(公告)日：2009-03-26
申请号：US11860840
申请日：2007-09-25
申请人： Brian J. Greene , Mahender Kumar
发明人： Brian J. Greene , Mahender Kumar
IPC分类号： H01L21/3205 , H01L27/01
CPC分类号： H01L27/1211 , H01L21/823807 , H01L21/823821 , H01L21/823842 , H01L21/845 , H01L29/66795 , H01L29/7851
摘要： A first high-k gate dielectric layer and a first metal gate layer are formed on first and second semiconductor fins. A first metal gate ring is formed on the first semiconductor fin. In one embodiment, the first high-k gate dielectric layer remains on the second semiconductor fin. A second metal gate layer and a silicon containing layer are deposited and patterned to form gate electrodes. In another embodiment, a second high-k dielectric layer replaces the first high-k dielectric layer over the second semiconductor fin, followed by formation of a second metal gate layer. A first electrode comprising a first gate dielectric and a first metal gate is formed on the first semiconductor fin, while a second electrode comprising a second gate dielectric and a second metal gate is formed on the second semiconductor fin. Absence of high-k gate dielectric materials on a gate wiring prevents increase in parasitic resistance.
摘要翻译：在第一和第二半导体鳍片上形成第一高k栅介质层和第一金属栅极层。第一金属栅环形成在第一半导体鳍上。在一个实施例中，第一高k栅介质层保留在第二半导体鳍片上。沉积第二金属栅极层和含硅层以形成栅电极。在另一个实施例中，第二高k电介质层替代第二半导体鳍片上的第一高k电介质层，随后形成第二金属栅极层。包括第一栅极电介质和第一金属栅极的第一电极形成在第一半导体鳍片上，而在第二半导体鳍片上形成包括第二栅极电介质和第二金属栅极的第二电极。在栅极布线上缺少高k栅极电介质材料可防止寄生电阻的增加。

9. 发明授权

US07943467B2 Structure and method to fabricate MOSFET with short gate 有权
标题翻译：用短栅制造MOSFET的结构和方法
公开(公告)号：US07943467B2
公开(公告)日：2011-05-17
申请号：US12016317
申请日：2008-01-18
申请人： Huilong Zhu , Brian J. Greene , Yanfeng Wang , Daewon Yang
发明人： Huilong Zhu , Brian J. Greene , Yanfeng Wang , Daewon Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/28079 , H01L21/28088 , H01L29/4966 , H01L29/4975 , H01L29/66545 , H01L29/6659 , Y10S257/901
摘要： A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.
摘要翻译：提供了一种制造半导体器件的方法，其在一个实施例中包括提供包括在衬底顶部的栅极结构的半导体器件，所述栅极结构包括包括上栅极导体和下栅极导体的双栅极导体，其中至少下部栅极导体包括含硅材料; 去除对下栅极导体选择性的上栅极导体; 在至少所述下栅极导体上沉积金属; 并从金属和下部栅极导体产生硅化物。在另一个实施例中，本发明的方法包括作为下栅极导体的金属。

10. 发明授权

US08039331B2 Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors 有权
标题翻译：用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法
公开(公告)号：US08039331B2
公开(公告)日：2011-10-18
申请号：US12120286
申请日：2008-05-14
申请人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
发明人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

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