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1. 发明申请

US20080170454A1 Sense amplifier with stages to reduce capacitance mismatch in current mirror load 有权
标题翻译：具有阶段的感应放大器，以减少电流镜像负载中的电容失配
公开(公告)号：US20080170454A1
公开(公告)日：2008-07-17
申请号：US11652770
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
摘要翻译：一种用于读取存储器单元状态的读出放大器电路。在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上不受由第一和第二级的瞬态特性提供的电容电流分量的影响。

2. 发明授权

US07522463B2 Sense amplifier with stages to reduce capacitance mismatch in current mirror load 有权
标题翻译：具有阶段的感应放大器，以减少电流镜像负载中的电容失配
公开(公告)号：US07522463B2
公开(公告)日：2009-04-21
申请号：US11652770
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre′
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre′
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
摘要翻译：一种用于读取存储器单元状态的读出放大器电路。在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上不受由第一和第二级的瞬态特性提供的电容电流分量的影响。

3. 发明申请

US20080164948A1 BIASING CURRENT TO SPEED UP CURRENT MIRROR SETTLING TIME 有权
标题翻译：偏移电流以加快电流反射时间
公开(公告)号：US20080164948A1
公开(公告)日：2008-07-10
申请号：US11619729
申请日：2007-01-04
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
IPC分类号： H03F3/04
CPC分类号： H03F3/343 , G09G3/20 , G09G3/3216 , G09G3/3225
摘要： A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.
摘要翻译：电流镜电路包括耦合到第二电流镜晶体管的第一电流镜晶体管。负载耦合到第二电流镜晶体管。第一电流源耦合到第一电流镜晶体管以引起偏置电流流过第一电流镜晶体管，并且第二电流源耦合到第二电流镜晶体管并且与负载并联以分流偏置电流远离负载。

4. 发明授权

US07522002B2 Biasing current to speed up current mirror settling time 有权
标题翻译：偏置电流以加快电流反射镜稳定时间
公开(公告)号：US07522002B2
公开(公告)日：2009-04-21
申请号：US11619729
申请日：2007-01-04
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
IPC分类号： H03F3/04
CPC分类号： H03F3/343 , G09G3/20 , G09G3/3216 , G09G3/3225
摘要： A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.
摘要翻译：电流镜电路包括耦合到第二电流镜晶体管的第一电流镜晶体管。负载耦合到第二电流镜晶体管。第一电流源耦合到第一电流镜晶体管以引起偏置电流流过第一电流镜晶体管，并且第二电流源耦合到第二电流镜晶体管并且与负载并联以分流偏置电流远离负载。

5. 发明授权

US07447071B2 Low voltage column decoder sharing a memory array p-well 有权
标题翻译：共享一个存储阵列p-well的低压列解码器
公开(公告)号：US07447071B2
公开(公告)日：2008-11-04
申请号：US11557627
申请日：2006-11-08
申请人： Massimiliano Frulio , Stefano Surico , Andrea Sacco , Davide Manfre
发明人： Massimiliano Frulio , Stefano Surico , Andrea Sacco , Davide Manfre
IPC分类号： G11C11/34
CPC分类号： G11C16/08
摘要： A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder. Each of the intermediate-level column decoders also has a high-voltage switch that is activated during a memory erase mode of operation to provide a high voltage to gate terminals of the intermediate-level column decoders.
摘要翻译：多个存储器子阵列形成在p阱区域中。每个存储器子阵列具有至少一个第一级列解码器，其包括也形成在p阱内的多个低压MOS选择晶体管。最后一级解码器形成在p阱区域外部，并且包括高电压MOS晶体管，以向读出放大器阵列之一提供输出信号。在存储器擦除操作模式期间，提供高电压以偏置p阱区域，并且激活多个高压开关以向第一级列解码器中的选择器晶体管的栅极端提供高电压。在第一级列解码器和最后一级列解码器之间的p阱中形成一个或多个中间级列解码器作为低电压选择晶体管。每个中间级列解码器还具有在存储器擦除操作模式期间激活的高压开关，以向中级列解码器的栅极端提供高电压。

6. 发明申请

US20050073355A1 HIGH PRECISION DIGITAL-TO-ANALOG CONVERTER WITH OPTIMIZED POWER CONSUMPTION 有权
标题翻译：具有优化功耗的高精度数字到模拟转换器
公开(公告)号：US20050073355A1
公开(公告)日：2005-04-07
申请号：US10753273
申请日：2004-01-07
申请人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
发明人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
IPC分类号： G05F1/10 , G05F3/02 , H02M20060101 , H02M3/07 , H02M5/42 , H03M1/76
CPC分类号： H02M3/07 , H03M1/765
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.
摘要翻译：一种具有双向切换装置的调节电荷泵电路，其在提供精确和稳定的电压输出的第一反馈通路与从电源提供具有低电流消耗的调节电压输出的第二反馈通路之间切换。第一反馈通道通过调节将电流吸引到电压输出的通过装置来保持精确的电压输出。第二反馈通道通过控制时钟输入到电荷泵的连接来调节电压输出。可变电阻用于设置电压输出的稳定电平。通过使用组合逻辑电路将数字输入信号转换成可变电阻器的控制信号，形成数模转换器。

7. 发明授权

US07158415B2 System for performing fast testing during flash reference cell setting 有权
标题翻译：在闪存参考单元设置期间执行快速测试的系统
公开(公告)号：US07158415B2
公开(公告)日：2007-01-02
申请号：US11089268
申请日：2005-03-24
申请人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
发明人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
IPC分类号： G11C16/10
CPC分类号： G11C29/028 , G11C16/04 , G11C29/24 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： An embedded circuit in a memory device is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells. An external test device programs at least one reference cell to a predetermined value. The embedded circuit uses the cell programmed by the external device as a comparative reference to program additional reference cells.
摘要翻译：使用存储器件中的嵌入式电路来代替外部测试装置来执行耗费时间的任务，例如参考单元设置期间的电压验证。外部测试装置将至少一个参考单元编程为预定值。嵌入式电路使用由外部设备编程的单元作为比较参考来编程附加参考单元。

8. 发明申请

US20060140030A1 System for performing fast testing during flash reference cell setting 有权
标题翻译：在闪存参考单元设置期间执行快速测试的系统
公开(公告)号：US20060140030A1
公开(公告)日：2006-06-29
申请号：US11089268
申请日：2005-03-24
申请人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
发明人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
IPC分类号： G11C29/00
CPC分类号： G11C29/028 , G11C16/04 , G11C29/24 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： An embedded circuit in a memory device is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells. An external test device programs at least one reference cell to a predetermined value. The embedded circuit uses the cell programmed by the external device as a comparative reference to program additional reference cells.
摘要翻译：使用存储器件中的嵌入式电路来代替外部测试装置来执行耗费时间的任务，例如参考单元设置期间的电压验证。外部测试装置将至少一个参考单元编程为预定值。嵌入式电路使用由外部设备编程的单元作为比较参考来编程附加参考单元。

9. 发明授权

US07049880B2 High precision digital-to-analog converter with optimized power consumption 有权
标题翻译：具有优化功耗的高精度数模转换器
公开(公告)号：US07049880B2
公开(公告)日：2006-05-23
申请号：US11119675
申请日：2005-05-02
申请人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
发明人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07 , H03M1/765
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.
摘要翻译：一种具有双向切换装置的调节电荷泵电路，其在提供精确和稳定的电压输出的第一反馈通路与从电源提供具有低电流消耗的调节电压输出的第二反馈通路之间切换。第一反馈通道通过调节将电流吸引到电压输出的通过装置来保持精确的电压输出。第二反馈通道通过控制时钟输入到电荷泵的连接来调节电压输出。可变电阻用于设置电压输出的稳定电平。通过使用组合逻辑电路将数字输入信号转换成可变电阻器的控制信号，形成数模转换器。

10. 发明授权

US07379338B2 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US07379338B2
公开(公告)日：2008-05-27
申请号：US11635160
申请日：2006-12-07
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/12 , G11C5/145 , G11C11/5628 , G11C16/04 , G11C16/30 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于为存储器单元编程提供调节的编程电压，用于编程路径电压降的调节的编程电压。

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