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1. 发明授权

US08953461B2 Method, device, and system for processing border gateway protocol route 有权
标题翻译：用于处理边界网关协议路由的方法，设备和系统
公开(公告)号：US08953461B2
公开(公告)日：2015-02-10
申请号：US13163133
申请日：2011-06-17
申请人： Lixin Zhang , Shuanglong Chen , Yuan Rao , Lei Fan , Boyan Tu , Jianwen Liu , Jianbin Xu , Qing Zeng
发明人： Lixin Zhang , Shuanglong Chen , Yuan Rao , Lei Fan , Boyan Tu , Jianwen Liu , Jianbin Xu , Qing Zeng
IPC分类号： H04L12/26 , H04L12/56 , H04L12/28 , H04L12/715 , H04L12/751
CPC分类号： H04L45/04 , H04L45/02
摘要： A method, device, and system for processing Border Gateway Protocol (BGP) route are provided, which relate to the field of network communication technologies. The method includes: receiving a BGP route sent by a BGP neighbor; obtaining a route prefix of the BGP route according to the BGP route; determining, according to the route prefix, a BGP route storing and processing module corresponding to the route prefix; and sending the BGP route to the determined BGP route storing and processing module, so that the BGP route storing and processing module processes the received BGP route. A device and a system for processing BGP route are also provided. Therefore, the processing efficiency of the BGP route is improved, and the high extensibility is realized.
摘要翻译：提供了一种处理边界网关协议（BGP）路由的方法，设备和系统，涉及网络通信技术领域。该方法包括：接收BGP邻居发送的BGP路由; 根据BGP路由获取BGP路由的路由前缀; 根据路由前缀确定与路由前缀对应的BGP路由存储和处理模块; 并将BGP路由发送到确定的BGP路由存储和处理模块，使BGP路由存储和处理模块处理接收到的BGP路由。还提供了一种用于处理BGP路由的设备和系统。因此，提高了BGP路由的处理效率，实现了高可扩展性。

2. 发明申请

US20110310903A1 METHOD, APPARATUS, AND SYSTEM FOR MIGRATING VPN ROUTING AND FORWARDING INSTANCES 审中-公开
标题翻译：用于迁移VPN路由和转发实例的方法，设备和系统
公开(公告)号：US20110310903A1
公开(公告)日：2011-12-22
申请号：US13224960
申请日：2011-09-02
申请人： Boyan Tu , Lixin Zhang , Shuanglong Chen , Jianwen Liu , Jianbin Xu , Xiaohui Liu
发明人： Boyan Tu , Lixin Zhang , Shuanglong Chen , Jianwen Liu , Jianbin Xu , Xiaohui Liu
IPC分类号： H04L12/56
CPC分类号： H04L45/586 , H04L45/04
摘要： A method, an apparatus and a system for migrating VPN Routing and Forwarding (VRF) instances are disclosed. The system includes: a first BGP process, configured to: send a VRF instance and configuration information of BGP peers in the VRF instance to a second Border Gateway Protocol (BGP) process; instruct a Transport Control Protocol (TCP) to back up a TCP link to the second BGP process in a hot backup mode, where the TCP link is related to peer sessions of the BGP peers in the VRF instance; and the second BGP process, configured to: receive routes in an Adjacent Ingress Routing Information Base (Adj-RIB-IN) sent by the first BGP process unit. In the embodiments of the present invention, BGP peers services of the VRF instance are not interrupted, and the sessions are not disconnected; a peer device cannot perceive the migration process of a router completely; and changed routing information in the migration process is updated after the migration.
摘要翻译：公开了用于迁移VPN路由和转发（VRF）实例的方法，装置和系统。该系统包括：第一个BGP进程，用于：将VRF实例中的BGP对等体的VRF实例和配置信息发送到第二个边界网关协议（BGP）进程; 指示传输控制协议（TCP）以热备份模式备份到第二BGP进程的TCP链路，其中TCP链路与VRF实例中的BGP对等体的对等体会话相关; 和第二BGP进程，被配置为：在第一BGP进程单元发送的相邻入口路由信息库（Adj-RIB-IN）中接收路由。在本发明实施例中，VRF实例的BGP对等体业务不中断，会话不断开; 对等设备无法完全了解路由器的迁移过程; 并且在迁移过程中更改路由信息在迁移之后被更新。

3. 发明授权

US07944926B2 Method and system for migrating a peer in a distributed BGP system 有权
标题翻译：在分布式BGP系统中迁移对等体的方法和系统
公开(公告)号：US07944926B2
公开(公告)日：2011-05-17
申请号：US12393289
申请日：2009-02-26
申请人： Lixin Zhang , Boyan Tu
发明人： Lixin Zhang , Boyan Tu
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04L45/56
摘要： A method for peer migration in a distributed Border Gateway Protocol (BGP) system includes: disconnecting a peer relationship between a source BGP process and a network device, wherein first routing information received from the network device is recorded in a forwarding instruction process; establishing a peer relationship between a target BGP process and the network device, and receiving second routing information from the network device; and updating the first routing information recorded in the forwarding instruction process according to the second routing information.
摘要翻译：一种分布式边界网关协议（BGP）系统中对等体迁移的方法，包括：断开源BGP进程与网络设备之间的对等体关系，其中从网络设备接收到的第一路由信息记录在转发指令过程中; 建立目标BGP进程与网络设备之间的对等体关系，并从网络设备接收第二路由信息; 以及根据第二路由信息来更新记录在转发指令处理中的第一路由信息。

4. 发明授权

US09197550B2 Method and device for determining forwarding rule for data packet 有权
标题翻译：确定数据包转发规则的方法和装置
公开(公告)号：US09197550B2
公开(公告)日：2015-11-24
申请号：US13513959
申请日：2009-12-17
申请人： Lixin Zhang , Duan Chen , Lijun Chen
发明人： Lixin Zhang , Duan Chen , Lijun Chen
IPC分类号： H04L12/28 , H04L12/723 , H04L12/46 , H04L12/721
CPC分类号： H04L45/50 , H04L12/4625 , H04L12/4641 , H04L45/66 , H04L45/68
摘要： A method and corresponding device for determining forwarding rule for data packet in Virtual Private LAN Service with Provider Backbone Bridge (PBB-VPLS) network are disclosed. In the method, a value in a backbone service instance identifier (I-SID) field of the received data packet is firstly examined, then a virtual split horizon group corresponding to the data packets is determined based on the I-SID value, wherein the virtual split horizon group defines a forwarding rule for the data packets between different pseudo wire ports of the PBB-VPLS network. With the dynamic split horizon group, the method dynamically adapts to different forwarding rules for multiple I-VPLS instances with different tree topologies, and is capable of supporting multiple I-VPLS instances with different root sites and tree topologies in one B-VPLS instance, thereby ensuring the stability of the backbone network and reducing the network operation cost.
摘要翻译：公开了一种用于确定具有提供商骨干桥（PBB-VPLS）网络的虚拟专用LAN服务中的数据分组的转发规则的方法和相应设备。在该方法中，首先检查接收到的数据分组的骨干服务实例标识符（I-SID）字段中的值，然后基于I-SID值确定与数据分组对应的虚拟水平分割组，其中，虚拟水平分割组为PBB-VPLS网络的不同伪线端口之间的数据包定义了转发规则。利用动态水平分割组，该方法动态适应不同树拓扑的多个I-VPLS实例的不同转发规则，并且能够在一个B-VPLS实例中支持具有不同根站点和树形拓扑的多个I-VPLS实例，从而确保骨干网的稳定性，降低网络运营成本。

5. 发明授权

US08966219B2 Address translation through an intermediate address space 有权
标题翻译：通过中间地址空间进行地址转换
公开(公告)号：US08966219B2
公开(公告)日：2015-02-24
申请号：US11928125
申请日：2007-10-30
申请人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/10
CPC分类号： G06F12/1063 , G06F12/1072
摘要： In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.
摘要翻译：在能够同时执行多个硬件执行线程的数据处理系统中，处理单元中的中间地址转换单元将存储器访问的有效地址转换为中间地址。使用中间地址访问高速缓冲存储器。响应于高速缓冲存储器中的缺失，中间地址被实现地址转换单元转换成实地址，该单元执行多个硬件执行线程的地址转换。使用实际地址访问系统内存。

6. 发明授权

US08909871B2 Data processing system and method for reducing cache pollution by write stream memory access patterns 有权
标题翻译：用于通过写入流存储器访问模式减少高速缓存污染的数据处理系统和方法
公开(公告)号：US08909871B2
公开(公告)日：2014-12-09
申请号：US11462115
申请日：2006-08-03
申请人： Ravi K. Arimilli , Francis P. O'Connell , Hazim Shafi , Derek E. Williams , Lixin Zhang
发明人： Ravi K. Arimilli , Francis P. O'Connell , Hazim Shafi , Derek E. Williams , Lixin Zhang
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0888
摘要： A data processing system includes a system memory and a cache hierarchy that caches contents of the system memory. According to one method of data processing, a storage modifying operation having a cacheable target real memory address is received. A determination is made whether or not the storage modifying operation has an associated bypass indication. In response to determining that the storage modifying operation has an associated bypass indication, the cache hierarchy is bypassed, and an update indicated by the storage modifying operation is performed in the system memory. In response to determining that the storage modifying operation does not have an associated bypass indication, the update indicated by the storage modifying operation is performed in the cache hierarchy.
摘要翻译：数据处理系统包括缓存系统存储器的内容的系统存储器和高速缓存层级。根据一种数据处理方法，接收具有可缓存目标实际存储器地址的存储修改操作。确定存储修改操作是否具有相关的旁路指示。响应于确定存储修改操作具有相关联的旁路指示，忽略高速缓存层级，并且在系统存储器中执行由存储修改操作指示的更新。响应于确定存储修改操作没有相关联的旁路指示，在高速缓存层级中执行由存储修改操作指示的更新。

7. 发明授权

US08843705B2 Read and write aware cache with a read portion and a write portion of a tag and status array 有权
标题翻译：具有读取部分和标签和状态数组的写入部分的读写感知高速缓存
公开(公告)号：US08843705B2
公开(公告)日：2014-09-23
申请号：US13572916
申请日：2012-08-13
申请人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F2212/271 , Y02D10/13
摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.
摘要翻译：在缓存中提供了一种机制，用于提供读写感知高速缓存。该机制将大型缓存分区分为常读区域和经常写区域。该机制将读/写频率视为非均匀缓存架构替换策略。经常写入的高速缓存行放置在更远的存储区之一中。经常读取的高速缓存行被放置在其中一个较近的存储体中。常读区域和经常写区域之间的大小比可以是静态的或动态的。经常读区域和经常写区域之间的边界可能是不同的或模糊的。

8. 发明授权

US08589665B2 Instruction set architecture extensions for performing power versus performance tradeoffs 失效
标题翻译：用于执行功率与性能折衷的指令集架构扩展
公开(公告)号：US08589665B2
公开(公告)日：2013-11-19
申请号：US12788940
申请日：2010-05-27
申请人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
发明人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
IPC分类号： G06F9/00
CPC分类号： G06F9/30083 , G06F1/3203 , G06F9/3013 , G06F9/30181 , G06F9/3836 , G06F9/3869 , G06F9/3885 , G06F11/302 , G06F11/3062 , G06F11/3096
摘要： Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.
摘要翻译：提供了用于处理数据处理系统的处理器中的指令的机制。这些机制操作以在数据处理系统的处理器中接收指令，该指令包括与指令相关联的功率/性能权衡信息。这些机制进一步操作以基于功率/性能折衷信息来确定功率/性能折衷优先级或标准，指定功率节省或关于指令的执行是否优先的性能。此外，机构根据功率/性能折衷优先级或基于指令的功率/性能折衷信息识别的标准处理指令。

9. 发明授权

US08482064B2 Termination for superjunction VDMOSFET 有权
标题翻译：端接VDMOSFET
公开(公告)号：US08482064B2
公开(公告)日：2013-07-09
申请号：US13493505
申请日：2012-06-11
申请人： Yangbo Yi , Haisong Li , Qin Wang , Ping Tao , Lixin Zhang
发明人： Yangbo Yi , Haisong Li , Qin Wang , Ping Tao , Lixin Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0653 , H01L29/0696
摘要： A termination for silicon superjunction VDMOSFET comprises heavily doped N-type silicon substrate which also works as drain region; drain metal is disposed on the back surface of the heavily doped N-type silicon substrate; an N-type silicon epitaxial layer is disposed on the heavily doped N-type silicon substrate; P-type silicon columns and N-type silicon columns are formed in the N-type silicon epitaxial layer, alternately arranged; a continuous silicon oxide layer is disposed on a part of silicon surface in the termination; structures that block the drift of mobile ions (several discontinuous silicon oxide layers arranged at intervals) are disposed on the other part of silicon surface in the termination. The structures that block the drift of mobile ions disposed in the termination region are able to effectively prevent movement of the mobile ions and improve the capability of the power device against the contamination induced by the mobile ions.
摘要翻译：硅超结VDMOSFET的终端包括也用作漏极区的重掺杂N型硅衬底; 漏极金属配置在重掺杂N型硅衬底的背表面上; 在重掺杂的N型硅衬底上设置N型硅外延层; 交替布置在N型硅外延层中形成P型硅柱和N型硅柱; 连续的氧化硅层设置在终端的硅表面的一部分上; 阻止移动离子漂移的结构（间隔布置的几个不连续的氧化硅层）设置在终端的硅表面的另一部分上。阻止设置在终端区域中的移动离子的漂移的结构能够有效地防止移动离子的移动，并提高功率器件抵抗由移动离子引起的污染的能力。

10. 发明授权

US08346988B2 Techniques for dynamically sharing a fabric to facilitate off-chip communication for multiple on-chip units 失效
标题翻译：用于动态共享结构以促进多个片上单元的片外通信的技术
公开(公告)号：US08346988B2
公开(公告)日：2013-01-01
申请号：US12786716
申请日：2010-05-25
申请人： Jian Li , William E. Speight , Lixin Zhang
发明人： Jian Li , William E. Speight , Lixin Zhang
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F1/3203 , G06F1/3253 , G06F9/5011 , Y02D10/151 , Y02D10/22
摘要： A technique for sharing a fabric to facilitate off-chip communication for on-chip units includes dynamically assigning a first unit that implements a first communication protocol to a first portion of the fabric when private fabrics are indicated for the on-chip units. The technique also includes dynamically assigning a second unit that implements a second communication protocol to a second portion of the fabric when the private fabrics are indicated for the on-chip units. In this case, the first and second units are integrated in a same chip and the first and second protocols are different. The technique further includes dynamically assigning, based on off-chip traffic requirements of the first and second units, the first unit or the second unit to the first and second portions of the fabric when the private fabrics are not indicated for the on-chip units.
摘要翻译：一种用于共享一个结构以促进片上单元的片外通信的技术包括：当针对片上单元指示专用结构时，动态分配实现第一通信协议的第一单元到该结构的第一部分。该技术还包括当为片上单元指示专用结构时，动态地将实现第二通信协议的第二单元分配给该结构的第二部分。在这种情况下，第一和第二单元集成在相同的芯片中，并且第一和第二协议是不同的。该技术还包括：当私有结构未被指示用于片上单元时，基于第一单元或第二单元的片外流量要求将第一单元或第二单元动态地分配给该结构的第一和第二部分。

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