专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08589665B2 Instruction set architecture extensions for performing power versus performance tradeoffs 失效
标题翻译：用于执行功率与性能折衷的指令集架构扩展
公开(公告)号：US08589665B2
公开(公告)日：2013-11-19
申请号：US12788940
申请日：2010-05-27
申请人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
发明人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
IPC分类号： G06F9/00
CPC分类号： G06F9/30083 , G06F1/3203 , G06F9/3013 , G06F9/30181 , G06F9/3836 , G06F9/3869 , G06F9/3885 , G06F11/302 , G06F11/3062 , G06F11/3096
摘要： Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.
摘要翻译：提供了用于处理数据处理系统的处理器中的指令的机制。这些机制操作以在数据处理系统的处理器中接收指令，该指令包括与指令相关联的功率/性能权衡信息。这些机制进一步操作以基于功率/性能折衷信息来确定功率/性能折衷优先级或标准，指定功率节省或关于指令的执行是否优先的性能。此外，机构根据功率/性能折衷优先级或基于指令的功率/性能折衷信息识别的标准处理指令。

2. 发明申请

US20110296149A1 Instruction Set Architecture Extensions for Performing Power Versus Performance Tradeoffs 失效
标题翻译：用于执行电力与性能权衡的指令集架构扩展
公开(公告)号：US20110296149A1
公开(公告)日：2011-12-01
申请号：US12788940
申请日：2010-05-27
申请人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
发明人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
IPC分类号： G06F9/318
CPC分类号： G06F9/30083 , G06F1/3203 , G06F9/3013 , G06F9/30181 , G06F9/3836 , G06F9/3869 , G06F9/3885 , G06F11/302 , G06F11/3062 , G06F11/3096
摘要： Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.
摘要翻译：提供了用于处理数据处理系统的处理器中的指令的机制。这些机制操作以在数据处理系统的处理器中接收指令，该指令包括与指令相关联的功率/性能权衡信息。这些机制进一步操作以基于功率/性能折衷信息来确定功率/性能折衷优先级或标准，指定功率节省或关于指令的执行是否优先的性能。此外，机构根据功率/性能折衷优先级或基于指令的功率/性能折衷信息识别的标准处理指令。

3. 发明授权

US08179674B2 Scalable space-optimized and energy-efficient computing system 失效
标题翻译：可扩展的空间优化和节能计算系统
公开(公告)号：US08179674B2
公开(公告)日：2012-05-15
申请号：US12789583
申请日：2010-05-28
申请人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Madhusudan K. Iyengar , Thomas W. Keller, Jr. , Jian Li , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
发明人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Madhusudan K. Iyengar , Thomas W. Keller, Jr. , Jian Li , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
IPC分类号： G06F1/20 , H05K7/20
CPC分类号： G06F1/20
摘要： A scalable space-optimized and energy-efficient computing system is provided. The computing system comprises a plurality of modular compartments in at least one level of a frame configured in a hexadron configuration. The computing system also comprises an air inlet, an air mixing plenum, and at least one fan. In the computing system the plurality of modular compartments are affixed above the air inlet, the air mixing plenum is affixed above the plurality of modular compartments, and the at least one fan is affixed above the air mixing plenum. When at least one module is inserted into one of the plurality of modular compartments, the module couples to a backplane within the frame.
摘要翻译：提供了可扩展的空间优化和节能计算系统。计算系统包括在六排配置中配置的框架的至少一个级别中的多个模块化隔间。计算系统还包括空气入口，空气混合增压室和至少一个风扇。在计算系统中，多个模块化隔间固定在空气入口上方，空气混合气室固定在多个模块化隔间上方，并且至少一个风扇固定在空气混合气室的上方。当至少一个模块被插入多个模块化隔间中的一个时，模块耦合到框架内的背板。

4. 发明申请

US20110292594A1 Scalable Space-Optimized and Energy-Efficient Computing System 失效
标题翻译：可扩展空间优化和节能计算系统
公开(公告)号：US20110292594A1
公开(公告)日：2011-12-01
申请号：US12789583
申请日：2010-05-28
申请人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Jian Li , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
发明人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Jian Li , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
IPC分类号： G06F1/20 , G06F13/00
CPC分类号： G06F1/20
摘要： A scalable space-optimized and energy-efficient computing system is provided. The computing system comprises a plurality of modular compartments in at least one level of a frame configured in a hexadron configuration. The computing system also comprises an air inlet, an air mixing plenum, and at least one fan. In the computing system the plurality of modular compartments are affixed above the air inlet, the air mixing plenum is affixed above the plurality of modular compartments, and the at least one fan is affixed above the air mixing plenum. When at least one module is inserted into one of the plurality of modular compartments, the module couples to a backplane within the frame.
摘要翻译：提供了可扩展的空间优化和节能计算系统。计算系统包括在六排配置中配置的框架的至少一个级别中的多个模块化隔间。计算系统还包括空气入口，空气混合增压室和至少一个风扇。在计算系统中，多个模块化隔间固定在空气入口上方，空气混合气室固定在多个模块化隔间上方，并且至少一个风扇固定在空气混合气室的上方。当至少一个模块被插入多个模块化隔间中的一个时，模块耦合到框架内的背板。

5. 发明申请

US20110292597A1 Stackable Module for Energy-Efficient Computing Systems 有权
标题翻译：用于节能计算系统的可堆叠模块
公开(公告)号：US20110292597A1
公开(公告)日：2011-12-01
申请号：US12789617
申请日：2010-05-28
申请人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
发明人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
IPC分类号： G06F1/20 , G06F13/00
CPC分类号： H05K7/20 , G06F1/181 , G06F1/20
摘要： A modular processing module is provided. The modular processing module comprises a set of processing module sides. Each processing module side comprises a circuit board, a plurality of connectors coupled to the circuit board, and a plurality of processing nodes coupled to the circuit board. Each processing module side in the set of processing module sides couples to another processing module side using at least one connector in the plurality of connectors such that, when all of the set of processing module sides are coupled together, the modular processing module is formed. The modular processing module comprises an exterior connection to a power source and a communication system.
摘要翻译：提供模块化处理模块。模块化处理模块包括一组处理模块侧面。每个处理模块侧包括电路板，耦合到电路板的多个连接器以及耦合到电路板的多个处理节点。处理模块组中的每个处理模块侧均使用多个连接器中的至少一个连接器耦合到另一个处理模块侧，使得当所有这组处理模块侧面耦合在一起时，形成模块化处理模块。模块化处理模块包括到电源和通信系统的外部连接。

6. 发明授权

US08358503B2 Stackable module for energy-efficient computing systems 有权
标题翻译：用于节能计算系统的可堆叠模块
公开(公告)号：US08358503B2
公开(公告)日：2013-01-22
申请号：US12789617
申请日：2010-05-28
申请人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, Jr. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
发明人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, Jr. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
IPC分类号： H05K7/20
CPC分类号： H05K7/20 , G06F1/181 , G06F1/20
摘要： A modular processing module is provided. The modular processing module comprises a set of processing module sides. Each processing module side comprises a circuit board, a plurality of connectors coupled to the circuit board, and a plurality of processing nodes coupled to the circuit board. Each processing module side in the set of processing module sides couples to another processing module side using at least one connector in the plurality of connectors such that, when all of the set of processing module sides are coupled together, the modular processing module is formed. The modular processing module comprises an exterior connection to a power source and a communication system.
摘要翻译：提供模块化处理模块。模块化处理模块包括一组处理模块侧面。每个处理模块侧包括电路板，耦合到电路板的多个连接器以及耦合到电路板的多个处理节点。处理模块组中的每个处理模块侧均使用多个连接器中的至少一个连接器耦合到另一个处理模块侧，使得当所有这组处理模块侧面耦合在一起时，形成模块化处理模块。模块化处理模块包括到电源和通信系统的外部连接。

7. 发明申请

US20110296097A1 Mechanisms for Reducing DRAM Power Consumption 失效
标题翻译：降低DRAM功耗的机制
公开(公告)号：US20110296097A1
公开(公告)日：2011-12-01
申请号：US12789019
申请日：2010-05-27
申请人： Elmootazbellah N. Elnozahy , Karthick Rajamani , William E. Speight , Lixin Zhang
发明人： Elmootazbellah N. Elnozahy , Karthick Rajamani , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , G11C11/406 , G11C11/4094 , G11C2211/4065 , G11C2211/4067 , Y02D10/13 , Y02D10/14
摘要： Mechanisms are provided for inhibiting precharging of memory cells of a dynamic random access memory (DRAM) structure. The mechanisms receive a command for accessing memory cells of the DRAM structure. The mechanisms further determine, based on the command, if precharging the memory cells following accessing the memory cells is to be inhibited. Moreover, the mechanisms send, in response to the determination indicating that precharging the memory cells is to be inhibited, a command to blocking logic of the DRAM structure to block precharging of the memory cells following accessing the memory cells.
摘要翻译：提供用于禁止动态随机存取存储器（DRAM）结构的存储器单元的预充电的机制。这些机制接收到用于访问DRAM结构的存储单元的命令。这些机制基于该命令进一步确定如果禁止在访问存储器单元之后对存储单元进行预充电。此外，机构响应于指示要禁止对存储器单元进行预充电的确定，发送阻止DRAM结构的逻辑以阻止访问存储器单元之后的存储器单元的预充电的命令。

8. 发明授权

US08250298B2 Mechanisms for reducing DRAM power consumption 失效
标题翻译：降低DRAM功耗的机制
公开(公告)号：US08250298B2
公开(公告)日：2012-08-21
申请号：US12789019
申请日：2010-05-27
申请人： Elmootazbellah N. Elnozahy , Karthick Rajamani , William E. Speight , Lixin Zhang
发明人： Elmootazbellah N. Elnozahy , Karthick Rajamani , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , G11C11/406 , G11C11/4094 , G11C2211/4065 , G11C2211/4067 , Y02D10/13 , Y02D10/14
摘要： Mechanisms are provided for inhibiting precharging of memory cells of a dynamic random access memory (DRAM) structure. The mechanisms receive a command for accessing memory cells of the DRAM structure. The mechanisms further determine, based on the command, if precharging the memory cells following accessing the memory cells is to be inhibited. Moreover, the mechanisms send, in response to the determination indicating that precharging the memory cells is to be inhibited, a command to blocking logic of the DRAM structure to block precharging of the memory cells following accessing the memory cells.
摘要翻译：提供用于禁止动态随机存取存储器（DRAM）结构的存储器单元的预充电的机制。这些机制接收到用于访问DRAM结构的存储单元的命令。这些机制基于该命令进一步确定如果禁止在访问存储器单元之后对存储单元进行预充电。此外，机构响应于指示要禁止对存储器单元进行预充电的确定，发送阻止DRAM结构的逻辑以阻止访问存储器单元之后的存储器单元的预充电的命令。

9. 发明授权

US08843705B2 Read and write aware cache with a read portion and a write portion of a tag and status array 有权
标题翻译：具有读取部分和标签和状态数组的写入部分的读写感知高速缓存
公开(公告)号：US08843705B2
公开(公告)日：2014-09-23
申请号：US13572916
申请日：2012-08-13
申请人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F2212/271 , Y02D10/13
摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.
摘要翻译：在缓存中提供了一种机制，用于提供读写感知高速缓存。该机制将大型缓存分区分为常读区域和经常写区域。该机制将读/写频率视为非均匀缓存架构替换策略。经常写入的高速缓存行放置在更远的存储区之一中。经常读取的高速缓存行被放置在其中一个较近的存储体中。常读区域和经常写区域之间的大小比可以是静态的或动态的。经常读区域和经常写区域之间的边界可能是不同的或模糊的。

10. 发明授权

US08346988B2 Techniques for dynamically sharing a fabric to facilitate off-chip communication for multiple on-chip units 失效
标题翻译：用于动态共享结构以促进多个片上单元的片外通信的技术
公开(公告)号：US08346988B2
公开(公告)日：2013-01-01
申请号：US12786716
申请日：2010-05-25
申请人： Jian Li , William E. Speight , Lixin Zhang
发明人： Jian Li , William E. Speight , Lixin Zhang
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F1/3203 , G06F1/3253 , G06F9/5011 , Y02D10/151 , Y02D10/22
摘要： A technique for sharing a fabric to facilitate off-chip communication for on-chip units includes dynamically assigning a first unit that implements a first communication protocol to a first portion of the fabric when private fabrics are indicated for the on-chip units. The technique also includes dynamically assigning a second unit that implements a second communication protocol to a second portion of the fabric when the private fabrics are indicated for the on-chip units. In this case, the first and second units are integrated in a same chip and the first and second protocols are different. The technique further includes dynamically assigning, based on off-chip traffic requirements of the first and second units, the first unit or the second unit to the first and second portions of the fabric when the private fabrics are not indicated for the on-chip units.
摘要翻译：一种用于共享一个结构以促进片上单元的片外通信的技术包括：当针对片上单元指示专用结构时，动态分配实现第一通信协议的第一单元到该结构的第一部分。该技术还包括当为片上单元指示专用结构时，动态地将实现第二通信协议的第二单元分配给该结构的第二部分。在这种情况下，第一和第二单元集成在相同的芯片中，并且第一和第二协议是不同的。该技术还包括：当私有结构未被指示用于片上单元时，基于第一单元或第二单元的片外流量要求将第一单元或第二单元动态地分配给该结构的第一和第二部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式