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1. 发明申请

US20100182033A1 TESTABLE INTEGRATED CIRCUIT AND TEST METHOD 审中-公开
标题翻译：可测试的集成电路和测试方法
公开(公告)号：US20100182033A1
公开(公告)日：2010-07-22
申请号：US12665722
申请日：2008-06-09
申请人： Laurent Souef , Emmanuel Alie
发明人： Laurent Souef , Emmanuel Alie
IPC分类号： G01R31/02
CPC分类号： G01R31/31715
摘要： An integrated circuit (100) is disclosed comprising a plurality of circuit portions (130), each of the circuit portions having an internal supply rail (170) coupled to a global supply rail (160) via a cluster (140) of switches (152; 154) coupled in parallel between the internal supply rail (170) and the global supply rail (160). Each cluster (140) of switches (152; 154) has a first switch (152) having a first size and a second switch (154) having a second size, a fault-free first switch (152) having a higher resistance than a fault-free second switch (154). The IC (100) further comprises a test arrangement for testing the respective clusters (140) of switches (152; 154) in a test mode. The test arrangement comprises a test control input; a test output coupled to the respective internal supply rails (170) and control means (110, 114, 116) coupled to the test control input for enabling a selected cluster (140) of switches (152; 154) in the test mode. The control means comprise first selection means (114) for selectively enabling the first switch (152) and second selection means (116) for selectively enabling the second switch (154) of the selected cluster (140) in the test mode. This arrangement allows for the accurate measurement of the resistance of power switches (152; 154) between a global power rail (160) and an internal power rail (170) of a circuit portion (130), thus facilitating the detection of both resistive and stuck-at faults in these switches (152; 154).
摘要翻译：公开了一种集成电路（100），其包括多个电路部分（130），每个电路部分具有经由开关（152）的簇（140）耦合到全局电源轨（160）的内部电源轨（170） ; 154），其并联连接在所述内部供应轨道（170）和所述全局供应轨道（160）之间。开关（152; 154）的每个簇（140）具有具有第一尺寸的第一开关（152）和具有第二尺寸的第二开关（154），无故障的第一开关（152）具有比无故障的第二开关（154）。 IC（100）还包括用于在测试模式下测试开关（152; 154）的相应簇（140）的测试装置。测试装置包括测试控制输入; 耦合到相应的内部电源轨（170）的测试输出和耦合到测试控制输入的控制装置（110,114,116），用于在测试模式下启用所选择的开关（152; 154）的集群（140）。控制装置包括用于选择性地启用第一开关（152）和第二选择装置（116）的第一选择装置（114），用于在测试模式中选择性地启用所选择的集群（140）的第二开关（154）。这种布置允许精确测量电路部分（130）的全局电力轨道（160）和内部电力轨道（170）之间的电力开关（152; 154）的电阻，从而有助于电阻和这些开关（152; 154）中存在故障。

2. 发明授权

US06970815B1 Method of discriminating between different types of scan failures, computer readable code to cause a display to graphically depict one or more simulated scan output data sets versus time and a computer implemented circuit simulation and fault detection system 失效
标题翻译：识别不同类型的扫描故障的方法，使得显示器以图形方式描绘一个或多个模拟扫描输出数据集与时间的计算机可读代码以及计算机实现的电路仿真和故障检测系统
公开(公告)号：US06970815B1
公开(公告)日：2005-11-29
申请号：US09443883
申请日：1999-11-18
申请人： Jerome Bombal , Laurent Souef
发明人： Jerome Bombal , Laurent Souef
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/3185 , G06F11/22 , G06F11/26 , G06F11/267 , G06F17/50
CPC分类号： G06F11/261 , G01R31/318591 , G06F11/267
摘要： A method of discriminating between different types of simulated scan failures includes simulating a scan enable signal to a circuit represented by a netlist corresponding to a scan chain coupled to combinatorial logic being tested, simulating initiation of a data capture cycle in the netlist corresponding to the scan chain, the data capture cycle simulating a series of scan flops from the scan chain being simulated together with the combinatorial logic and simulating scanning data out from each flop in the scan chain and into a test program. The test program extracts the simulated scan flops and graphically displays the simulated scan flops versus time.
摘要翻译：识别不同类型的模拟扫描故障的方法包括：将扫描使能信号模拟到由与被测试的组合逻辑耦合的扫描链相对应的网表所代表的电路，模拟与扫描相对应的网表中的数据捕获周期的启动数据捕获周期模拟来自扫描链的一系列扫描触发器与组合逻辑一起模拟，并从扫描链中的每个触发器模拟扫描数据并进入测试程序。测试程序提取模拟的扫描触发器，并以图形方式显示模拟的扫描触发器与时间。

3. 发明授权

US5960052A Low power scannable counter 失效
标题翻译：低功率可扫描计数器
公开(公告)号：US5960052A
公开(公告)日：1999-09-28
申请号：US62312
申请日：1998-04-17
申请人： Jerome Bombal , Laurent Souef
发明人： Jerome Bombal , Laurent Souef
IPC分类号： G01R31/317 , G01R31/3185 , G06M3/00
CPC分类号： G01R31/31721 , G01R31/318527
摘要： A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Each of the stages or cells comprises a flip-flop and a multiplexer which together operate as a toggle flip-flop only when all of the previous flip-flops are set. The result is that the flip-flop clock is forced high preventing any transition of the flip-flop internal clock tree for all stages or cells where the output is low. Thus, no power consumption of such stages takes place during functional operation. In the scan test mode, the counter operates as a shift register and it is fully testable.
摘要翻译：低功耗可扫描异步计数器是完全可测试的，并且在功能模式中消耗低功率的是由通过NOR门电路级联的反电池单元组成的，每个阶段或单元对其施加时钟信号。每个级或单元包括触发器和多路复用器，其仅在所有先前的触发器都被设置时一起用作触发触发器。结果是触发器时钟被强制为高，防止触发器内部时钟树对于输出低的所有级或单元的任何转换。因此，在功能操作期间不会发生这种阶段的功耗。在扫描测试模式下，计数器作为移位寄存器运行，它是完全可测试的。

4. 发明授权

US07870452B2 Scan testing methods 失效
标题翻译：扫描测试方法
公开(公告)号：US07870452B2
公开(公告)日：2011-01-11
申请号：US12065935
申请日：2006-09-07
申请人： Laurent Souef , Didier Gayraud
发明人： Laurent Souef , Didier Gayraud
IPC分类号： G01R31/28
CPC分类号： G01R31/318594
摘要： A method of testing an integrated circuit, comprises providing a test vector to a shift register arrangement by providing test vector bits in series into the shift register arrangement (20) timed with a first, scan, clock signal (42). The test vector bits are passed between adjacent portions of the shift register arrangement timed with the first clock signal (42) and an output response of the integrated circuit to the test vector is provided and analyzed. The output response of the integrated circuit to the test vector is provided under the control of a second clock signal (56) which is slower than the first clock signal. This testing method speeds up the process by increasing the speed of shifting test vectors and results into and out of the shift register, but without comprising the stability of the testing process. Furthermore, the method can be implemented without requiring additional complexity of the testing circuitry to be integrated onto the circuit substrate.
摘要翻译：一种测试集成电路的方法，包括：通过将测试向量位串联提供到与第一扫描时钟信号（42）定时的移位寄存器装置（20）中，向移位寄存器装置提供测试矢量。测试矢量位在与第一时钟信号（42）定时的移位寄存器配置的相邻部分之间通过，并且提供和分析集成电路对测试矢量的输出响应。在比第一时钟信号慢的第二时钟信号（56）的控制下提供集成电路对测试矢量的输出响应。该测试方法通过提高将测试向量和结果移入和移出移位寄存器的速度，但不包括测试过程的稳定性来加快处理速度。此外，可以实现该方法，而不需要将测试电路的额外复杂度集成到电路基板上。

5. 发明申请

US20050180196A1 Cell with fixed output voltage for integrated circuit 有权
标题翻译：具有固定输出电压的电池用于集成电路
公开(公告)号：US20050180196A1
公开(公告)日：2005-08-18
申请号：US10514902
申请日：2003-05-15
申请人： Patrick Da Silva , Laurent Souef
发明人： Patrick Da Silva , Laurent Souef
IPC分类号： H01L27/04 , G01R31/3185 , H01L21/822 , H03K17/00 , H03K19/00 , G11C11/00
CPC分类号： G01R31/318541 , G01R31/318536 , G01R31/318572
摘要： The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell (34) which comprises a flipflop (11) and means (31) able to set the output voltage of the cell when the circuit is in the operation mode. These means for setting the output voltage are controlled by a control signal (15) which depends on the mode signal that indicates whether the signal is in the test mode or in the operation mode.
摘要翻译：本发明涉及可测试的集成电路。为了在这种电路的某些点处替换接地和VDD，该电路包括一个单元（34），该单元包括一个触发器（11）和一个装置（31），当电路处于操作模式。用于设定输出电压的这些装置由控制信号（15）控制，控制信号（15）取决于指示信号是处于测试模式还是处于操作模式的模式信号。

6. 发明授权

US06311318B1 Design for test area optimization algorithm 失效
标题翻译：设计测试区域优化算法
公开(公告)号：US06311318B1
公开(公告)日：2001-10-30
申请号：US09353306
申请日：1999-07-13
申请人： Laurent Souef , Jerome Bombal , Bernard Ginetti
发明人： Laurent Souef , Jerome Bombal , Bernard Ginetti
IPC分类号： G06F1750
CPC分类号： G01R31/318342
摘要： A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design. The processing circuitry is configured to reduce layout area used during scan insertion, and is operative to: a) identify logic registers of a proposed integrated circuit design that are stitched as a shift register; b) use the ATPG algorithm to transform identified logical registers into scan equivalent logical registers; c) stitch scan equivalent logical registers in an order in which the scan equivalent logical registers were stitched; d) identify stitched scan equivalent logical registers having a same net on both an SI port and a D port; and e) replace the stitched scan equivalent logical registers having the same net on both the SI port and D port. A method is also provided for reducing layout area during test insertion when using an ATPG program to design an integrated circuit having design-for-testability features.
摘要翻译：计算机实现的电路合成系统包括存储器，自动测试模式生成（ATPG）算法和处理电路。存储器被配置为提供数据库，并且可操作地存储包括设计中的集成电路的网络的网表。自动测试模式生成（ATPG）算法可用于设计和测试集成电路设计。处理电路被配置为减少在扫描插入期间使用的布局区域，并且可操作以：a）识别作为移位寄存器缝合的所提出的集成电路设计的逻辑寄存器; b）使用ATPG算法将识别的逻辑寄存器转换为扫描等效逻辑寄存器; c）以扫描等效逻辑寄存器被缝合的顺序针对等效的逻辑寄存器进行扫描; d）在SI端口和D端口上识别具有相同网络的缝合扫描等效逻辑寄存器; 和e）在SI端口和D端口上替换具有相同网络的缝合扫描等效逻辑寄存器。还提供了一种方法，用于在使用ATPG程序设计具有设计可测试性特征的集成电路时减少测试插入期间的布局面积。

7. 发明申请

US20090051385A1 Cell with Fixed Output Voltage for Integrated Circuit 有权
标题翻译：用于集成电路的固定输出电压的单元
公开(公告)号：US20090051385A1
公开(公告)日：2009-02-26
申请号：US12262912
申请日：2008-10-31
申请人： Patrick Da Silva , Laurent Souef
发明人： Patrick Da Silva , Laurent Souef
IPC分类号： H03K19/20 , H03K19/003
CPC分类号： G01R31/318541 , G01R31/318536 , G01R31/318572
摘要： The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell (34) which comprises a flipflop (11) and means (31) able to set the output voltage of the cell when the circuit is in the operation mode. These means for setting the output voltage are controlled by a control signal (15) which depends on the mode signal that indicates whether the signal is in the test mode or in the operation mode.
摘要翻译：本发明涉及可测试的集成电路。为了在这种电路的某些点处替换接地和VDD，该电路包括一个单元（34），该单元包括一个触发器（11）和一个装置（31），当电路处于操作模式。用于设定输出电压的这些装置由控制信号（15）控制，控制信号（15）取决于指示信号是处于测试模式还是处于操作模式的模式信号。

8. 发明申请

US20080250288A1 Scan Testing Methods 失效
标题翻译：扫描测试方法
公开(公告)号：US20080250288A1
公开(公告)日：2008-10-09
申请号：US12065935
申请日：2006-09-07
申请人： Laurent Souef , Didier Gayraud
发明人： Laurent Souef , Didier Gayraud
IPC分类号： G01R31/28 , G06F11/25
CPC分类号： G01R31/318594
摘要： A method of testing an integrated circuit, comprises providing a test vector to a shift register arrangement by providing test vector bits in series into the shift register arrangement (20) timed with a first, scan, clock signal (42). The test vector bits are passed between adjacent portions of the shift register arrangement timed with the first clock signal (42) and an output response of the integrated circuit to the test vector is provided and analyzed. The output response of the integrated circuit to the test vector is provided under the control of a second clock signal (56) which is slower than the first clock signal. This testing method speeds up the process by increasing the speed of shifting test vectors and results into and out of the shift register, but without comprising the stability of the testing process. Furthermore, the method can be implemented without requiring additional complexity of the testing circuitry to be integrated onto the circuit substrate.
摘要翻译：一种测试集成电路的方法，包括：通过将测试向量位串联提供到与第一扫描时钟信号（42）定时的移位寄存器装置（20）中，向移位寄存器装置提供测试矢量。测试矢量位在与第一时钟信号（42）定时的移位寄存器配置的相邻部分之间通过，并且提供和分析集成电路对测试矢量的输出响应。在比第一时钟信号慢的第二时钟信号（56）的控制下提供集成电路对测试矢量的输出响应。该测试方法通过提高将测试向量和结果移入和移出移位寄存器的速度，但不包括测试过程的稳定性来加快处理速度。此外，可以实现该方法，而不需要将测试电路的额外复杂度集成到电路基板上。

9. 发明授权

US6141782A Pseudo-scan testing using hardware-accessible IC structures 失效
标题翻译：使用硬件可访问IC结构的伪扫描测试
公开(公告)号：US6141782A
公开(公告)日：2000-10-31
申请号：US52796
申请日：1998-03-31
申请人： Jerome Bombal , Laurent Souef
发明人： Jerome Bombal , Laurent Souef
IPC分类号： G01R31/3181 , G01R31/28
CPC分类号： G01R31/31813
摘要： The present invention, generally speaking, provides an integrated circuit testing technique in which hardware accessibility of selected components is exploited in order to avoid scan insertion overhead but achieve as good or better fault coverage than if scan insertion had been used. The term "pseudo-scan" is used to refer to the use of read and write instructions to achieve the equivalent effect as scan insertion without the addition of scan flops. Existing ATPG tools may be used without modification by performing scan insertion on a "dummy" circuit and performing ATPG on the scan-augmented dummy circuit. The resulting ATPG vectors are then modified to perform pseudo scan of selected components of the original circuit.
摘要翻译：本发明一般地提供一种集成电路测试技术，其中利用所选组件的硬件可访问性，以避免扫描插入开销，但是实现与使用扫描插入相比好或更好的故障覆盖。术语“伪扫描”用于指使用读取和写入指令来实现与扫描插入相同的效果，而不添加扫描触发器。可以通过在“虚拟”电路上执行扫描插入并且在扫描增加的虚拟电路上执行ATPG来使用现有的ATPG工具。然后对所得到的ATPG载体进行修改以对原始电路的选定部件执行伪扫描。

10. 发明授权

US5783874A Keypad handling circuits 失效
标题翻译：键盘处理电路
公开(公告)号：US5783874A
公开(公告)日：1998-07-21
申请号：US643756
申请日：1996-05-06
申请人： Philippe Gaglione , Laurent Souef , John Whittle
发明人： Philippe Gaglione , Laurent Souef , John Whittle
IPC分类号： G06F3/023 , H03K17/967 , H03M11/20 , H01H19/04
CPC分类号： H03M11/20 , Y10T307/74 , Y10T307/747 , Y10T307/951
摘要： A key handling circuit for a switching matrix having row and column conductors includes bidirectional drives for the row conductors and the column conductors. The row drive and the column drive are in a low conductive condition except when a relevant key switch is activated. The row drive provides a current input for the column drive in one phase of operation and the column drive provides a current input for a row drive in a second phase of operation.
摘要翻译：具有行和列导体的开关矩阵的键处理电路包括用于行导体和列导体的双向驱动器。行驱动器和列驱动器处于低导通状态，除了相关键开关被激活之后。行驱动器在一个操作阶段为列驱动器提供电流输入，列驱动器在第二个操作阶段为行驱动器提供电流输入。

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