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1. 发明授权

US6141782A Pseudo-scan testing using hardware-accessible IC structures 失效
标题翻译：使用硬件可访问IC结构的伪扫描测试
公开(公告)号：US6141782A
公开(公告)日：2000-10-31
申请号：US52796
申请日：1998-03-31
申请人： Jerome Bombal , Laurent Souef
发明人： Jerome Bombal , Laurent Souef
IPC分类号： G01R31/3181 , G01R31/28
CPC分类号： G01R31/31813
摘要： The present invention, generally speaking, provides an integrated circuit testing technique in which hardware accessibility of selected components is exploited in order to avoid scan insertion overhead but achieve as good or better fault coverage than if scan insertion had been used. The term "pseudo-scan" is used to refer to the use of read and write instructions to achieve the equivalent effect as scan insertion without the addition of scan flops. Existing ATPG tools may be used without modification by performing scan insertion on a "dummy" circuit and performing ATPG on the scan-augmented dummy circuit. The resulting ATPG vectors are then modified to perform pseudo scan of selected components of the original circuit.
摘要翻译：本发明一般地提供一种集成电路测试技术，其中利用所选组件的硬件可访问性，以避免扫描插入开销，但是实现与使用扫描插入相比好或更好的故障覆盖。术语“伪扫描”用于指使用读取和写入指令来实现与扫描插入相同的效果，而不添加扫描触发器。可以通过在“虚拟”电路上执行扫描插入并且在扫描增加的虚拟电路上执行ATPG来使用现有的ATPG工具。然后对所得到的ATPG载体进行修改以对原始电路的选定部件执行伪扫描。

2. 发明申请

US20050114612A1 Scan testable first-in first-out architecture 审中-公开
标题翻译：扫描可测试的先进先出架构
公开(公告)号：US20050114612A1
公开(公告)日：2005-05-26
申请号：US10828992
申请日：2004-04-21
申请人： Jerome Bombal
发明人： Jerome Bombal
IPC分类号： G11C29/00 , G06F12/00
CPC分类号： G11C29/003
摘要： An electronic device (10). The device comprises a memory structure (12), which comprises an integer M of memory word slots. Each memory word slot is operable to store an integer N of bits. The device also comprises a scan storage circuit (18), operable to receive a scan word having a number of bits less than M×N. The device also comprises control circuitry (16) for causing successive scan words to be written into the scan storage circuit, for causing successive scan words to be written from the scan storage circuit into the memory structure, and for causing successive scan words to be read from the memory structure into the scan storage circuit.
摘要翻译：电子设备（10）。该设备包括存储器结构（12），其包括整数M的存储器字槽。每个存储器字槽可操作以存储整数N的位。该装置还包括扫描存储电路（18），其可操作以接收具有小于M×N的位数的扫描字。该装置还包括用于使连续扫描字被写入扫描存储电路的控制电路（16），用于使连续的扫描字从扫描存储电路写入存储器结构，并用于使连续扫描字被读取从存储器结构到扫描存储电路。

3. 发明授权

US06311318B1 Design for test area optimization algorithm 失效
标题翻译：设计测试区域优化算法
公开(公告)号：US06311318B1
公开(公告)日：2001-10-30
申请号：US09353306
申请日：1999-07-13
申请人： Laurent Souef , Jerome Bombal , Bernard Ginetti
发明人： Laurent Souef , Jerome Bombal , Bernard Ginetti
IPC分类号： G06F1750
CPC分类号： G01R31/318342
摘要： A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design. The processing circuitry is configured to reduce layout area used during scan insertion, and is operative to: a) identify logic registers of a proposed integrated circuit design that are stitched as a shift register; b) use the ATPG algorithm to transform identified logical registers into scan equivalent logical registers; c) stitch scan equivalent logical registers in an order in which the scan equivalent logical registers were stitched; d) identify stitched scan equivalent logical registers having a same net on both an SI port and a D port; and e) replace the stitched scan equivalent logical registers having the same net on both the SI port and D port. A method is also provided for reducing layout area during test insertion when using an ATPG program to design an integrated circuit having design-for-testability features.
摘要翻译：计算机实现的电路合成系统包括存储器，自动测试模式生成（ATPG）算法和处理电路。存储器被配置为提供数据库，并且可操作地存储包括设计中的集成电路的网络的网表。自动测试模式生成（ATPG）算法可用于设计和测试集成电路设计。处理电路被配置为减少在扫描插入期间使用的布局区域，并且可操作以：a）识别作为移位寄存器缝合的所提出的集成电路设计的逻辑寄存器; b）使用ATPG算法将识别的逻辑寄存器转换为扫描等效逻辑寄存器; c）以扫描等效逻辑寄存器被缝合的顺序针对等效的逻辑寄存器进行扫描; d）在SI端口和D端口上识别具有相同网络的缝合扫描等效逻辑寄存器; 和e）在SI端口和D端口上替换具有相同网络的缝合扫描等效逻辑寄存器。还提供了一种方法，用于在使用ATPG程序设计具有设计可测试性特征的集成电路时减少测试插入期间的布局面积。

4. 发明授权

US06970815B1 Method of discriminating between different types of scan failures, computer readable code to cause a display to graphically depict one or more simulated scan output data sets versus time and a computer implemented circuit simulation and fault detection system 失效
标题翻译：识别不同类型的扫描故障的方法，使得显示器以图形方式描绘一个或多个模拟扫描输出数据集与时间的计算机可读代码以及计算机实现的电路仿真和故障检测系统
公开(公告)号：US06970815B1
公开(公告)日：2005-11-29
申请号：US09443883
申请日：1999-11-18
申请人： Jerome Bombal , Laurent Souef
发明人： Jerome Bombal , Laurent Souef
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/3185 , G06F11/22 , G06F11/26 , G06F11/267 , G06F17/50
CPC分类号： G06F11/261 , G01R31/318591 , G06F11/267
摘要： A method of discriminating between different types of simulated scan failures includes simulating a scan enable signal to a circuit represented by a netlist corresponding to a scan chain coupled to combinatorial logic being tested, simulating initiation of a data capture cycle in the netlist corresponding to the scan chain, the data capture cycle simulating a series of scan flops from the scan chain being simulated together with the combinatorial logic and simulating scanning data out from each flop in the scan chain and into a test program. The test program extracts the simulated scan flops and graphically displays the simulated scan flops versus time.
摘要翻译：识别不同类型的模拟扫描故障的方法包括：将扫描使能信号模拟到由与被测试的组合逻辑耦合的扫描链相对应的网表所代表的电路，模拟与扫描相对应的网表中的数据捕获周期的启动数据捕获周期模拟来自扫描链的一系列扫描触发器与组合逻辑一起模拟，并从扫描链中的每个触发器模拟扫描数据并进入测试程序。测试程序提取模拟的扫描触发器，并以图形方式显示模拟的扫描触发器与时间。

5. 发明授权

US5960052A Low power scannable counter 失效
标题翻译：低功率可扫描计数器
公开(公告)号：US5960052A
公开(公告)日：1999-09-28
申请号：US62312
申请日：1998-04-17
申请人： Jerome Bombal , Laurent Souef
发明人： Jerome Bombal , Laurent Souef
IPC分类号： G01R31/317 , G01R31/3185 , G06M3/00
CPC分类号： G01R31/31721 , G01R31/318527
摘要： A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Each of the stages or cells comprises a flip-flop and a multiplexer which together operate as a toggle flip-flop only when all of the previous flip-flops are set. The result is that the flip-flop clock is forced high preventing any transition of the flip-flop internal clock tree for all stages or cells where the output is low. Thus, no power consumption of such stages takes place during functional operation. In the scan test mode, the counter operates as a shift register and it is fully testable.
摘要翻译：低功耗可扫描异步计数器是完全可测试的，并且在功能模式中消耗低功率的是由通过NOR门电路级联的反电池单元组成的，每个阶段或单元对其施加时钟信号。每个级或单元包括触发器和多路复用器，其仅在所有先前的触发器都被设置时一起用作触发触发器。结果是触发器时钟被强制为高，防止触发器内部时钟树对于输出低的所有级或单元的任何转换。因此，在功能操作期间不会发生这种阶段的功耗。在扫描测试模式下，计数器作为移位寄存器运行，它是完全可测试的。

6. 发明授权

US07203803B2 Overflow protected first-in first-out architecture 有权
标题翻译：溢出保护先进先出架构
公开(公告)号：US07203803B2
公开(公告)日：2007-04-10
申请号：US10773482
申请日：2004-02-06
申请人： Jerome Bombal
发明人： Jerome Bombal
IPC分类号： G06F12/02
CPC分类号： G06F5/14
摘要： An electronic device (10). The device comprises an input (16I) for receiving successive data words, wherein each data word of the successive data words comprises a plurality of bits. The device also comprises a memory structure (12) comprising a plurality of memory word addresses, wherein each memory word address corresponds to a storage structure operable to store a data word having the plurality of bits. The device also comprises control circuitry (14, 16), operable during a non-overflow condition of the memory structure, for writing successive ones of received data words into respective successive ones of the memory word addresses. Finally, the device also comprises control circuitry (14, 16), operable during an overflow condition of the memory structure, for writing each data word in successive ones of received data words across multiple ones of the memory word addresses.
摘要翻译：电子设备（10）。该装置包括用于接收连续数据字的输入端（16I），其中连续数据字的每个数据字包括多个位。该设备还包括一个包括多个存储器字地址的存储器结构（12），其中每个存储器字地址对应于可操作以存储具有多个位的数据字的存储结构。该装置还包括在存储器结构的非溢出状态期间可操作的控制电路（14,16），用于将接收到的数据字的连续的一个写入相应的连续的存储器字地址。最后，该装置还包括在存储器结构的溢出状态期间可操作的控制电路（14,16），用于将多个接收的数据字中的每个数据字写入多个存储器字地址。

7. 发明申请

US20050033907A1 Overflow protected first-in first-out architecture 有权
标题翻译：溢出保护先进先出架构
公开(公告)号：US20050033907A1
公开(公告)日：2005-02-10
申请号：US10773482
申请日：2004-02-06
申请人： Jerome Bombal
发明人： Jerome Bombal
IPC分类号： G06F5/06 , G06F5/14 , G06F12/00
CPC分类号： G06F5/14
摘要： An electronic device (10). The device comprises an input (16I) for receiving successive data words, wherein each data word of the successive data words comprises a plurality of bits. The device also comprises a memory structure (12) comprising a plurality of memory word addresses, wherein each memory word address corresponds to a storage structure operable to store a data word having the plurality of bits. The device also comprises control circuitry (14, 16), operable during a non-overflow condition of the memory structure, for writing successive ones of received data words into respective successive ones of the memory word addresses. Finally, the device also comprises control circuitry (14, 16), operable during an overflow condition of the memory structure, for writing each data word in successive ones of received data words across multiple ones of the memory word addresses
摘要翻译：电子设备（10）。该装置包括用于接收连续数据字的输入端（16I），其中连续数据字的每个数据字包括多个位。该设备还包括一个包括多个存储器字地址的存储器结构（12），其中每个存储器字地址对应于可操作以存储具有多个位的数据字的存储结构。该装置还包括在存储器结构的非溢出状态期间可操作的控制电路（14,16），用于将接收到的数据字的连续的一个写入相应的连续的存储器字地址。最后，该设备还包括在存储器结构的溢出状态期间可操作的控制电路（14,16），用于将多个接收数据字中的每个数据字跨越多个存储器字地址

8. 发明授权

US06671870B2 Computer implemented circuit synthesis system 失效
标题翻译：计算机实现电路综合系统
公开(公告)号：US06671870B2
公开(公告)日：2003-12-30
申请号：US09953020
申请日：2001-09-10
申请人： Laurent Souef , Jerome Bombal , Bernard Ginetti
发明人： Laurent Souef , Jerome Bombal , Bernard Ginetti
IPC分类号： G06F1750
CPC分类号： G01R31/318342
摘要： A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design. The processing circuitry is configured to reduce layout area used during scan insertion, and is operative to: a) identify logic registers of a proposed integrated circuit design that are stitched as a shift register; b) use the ATPG algorithm to transform identified logical registers into scan equivalent logical registers; c) stitch scan equivalent logical registers in an order in which the scan equivalent logical registers were stitched; d) identify stitched scan equivalent logical registers having a same net on both an SI port and a D port; and e) replace the stitched scan equivalent logical registers having the same net on both the SI port and D port. A method is also provided for reducing layout area during test insertion when using an ATPG program to design an integrated circuit having design-for-testability features.
摘要翻译：计算机实现的电路合成系统包括存储器，自动测试模式生成（ATPG）算法和处理电路。存储器被配置为提供数据库，并且可操作地存储包括设计中的集成电路的网络的网表。自动测试模式生成（ATPG）算法可用于设计和测试集成电路设计。处理电路被配置为减少在扫描插入期间使用的布局区域，并且可操作以：a）识别作为移位寄存器缝合的所提出的集成电路设计的逻辑寄存器; b）使用ATPG算法将识别的逻辑寄存器转换为扫描等效逻辑寄存器; c）以扫描等效逻辑寄存器被缝合的顺序针对等效的逻辑寄存器进行扫描; d）在SI端口和D端口上识别具有相同网络的缝合扫描等效逻辑寄存器; 和e）在SI端口和D端口上替换具有相同网络的缝合扫描等效逻辑寄存器。还提供了一种方法，用于在使用ATPG程序设计具有设计可测试性特征的集成电路时减少测试插入期间的布局面积。

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