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1. 发明申请

US20080088339A1 Hard Macro with Configurable Side Input/Output Terminals, for a Subsystem 有权
标题翻译：具有可配置侧输入/输出端子的硬宏，用于子系统
公开(公告)号：US20080088339A1
公开(公告)日：2008-04-17
申请号：US11576685
申请日：2005-09-21
申请人： Caroline Carin , Emmanuel Alie
发明人： Caroline Carin , Emmanuel Alie
IPC分类号： G06F17/50 , H03K19/173
CPC分类号： G06F15/7832
摘要： A hard macro device (HMD), for a subsystem (TMi) such as a data processor, comprises a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time critical input data to be processed and at least one time critical output terminal (COT) adapted to deliver time critical output data it has processed. The processing core (C) is surrounded at least partly by a connecting interface zone (CIZ) comprising i) at least one input group of at least two time critical auxiliary input terminals (AITj), located at chosen locations and adapted to receive time critical input data to be processed, and/or at least one output group of at least two time critical auxiliary output terminals (AOTk), located at chosen locations and adapted to deliver processed time critical output data, ii) an input connecting means (LO) for connecting each time critical auxiliary input terminal (AITj) of this input group to the time critical input terminal (CIT), and/or iii) an output connecting means (Bk) for connecting the time critical output terminal (COT) to each time critical auxiliary output terminal (AOTk) of this output group.
摘要翻译：用于诸如数据处理器的子系统（TMi）的硬宏设备（HMD）包括设置有至少一个时间关键输入端（CIT）的处理核心（C），其适于将时间关键输入数据馈送到处理的和至少一个时间的关键输出端（COT），其适于传送其处理的时间关键输出数据。所述处理核心（C）至少部分地由连接接口区域（CIZ）包围，所述连接接口区域（CIZ）包括：i）至少两个至少两个时间关键的辅助输入端子（AITj）的至少一个输入组，位于所选择的位置并适于接收时间关键输入数据，以及/或至少两个时间关键辅助输出终端（AOTk）的至少一个输出组，位于所选位置并且适于提供处理的时间关键输出数据，ii）输入连接装置（LO）用于将该输入组的每个关键辅助输入端子（AITj）连接到时间关键输入端子（CIT），和/或iii）用于将时间关键输出端子（COT）连接到每个时间的输出连接装置（Bk）该输出组的关键辅助输出端子（AOTk）。

2. 发明申请

US20100182033A1 TESTABLE INTEGRATED CIRCUIT AND TEST METHOD 审中-公开
标题翻译：可测试的集成电路和测试方法
公开(公告)号：US20100182033A1
公开(公告)日：2010-07-22
申请号：US12665722
申请日：2008-06-09
申请人： Laurent Souef , Emmanuel Alie
发明人： Laurent Souef , Emmanuel Alie
IPC分类号： G01R31/02
CPC分类号： G01R31/31715
摘要： An integrated circuit (100) is disclosed comprising a plurality of circuit portions (130), each of the circuit portions having an internal supply rail (170) coupled to a global supply rail (160) via a cluster (140) of switches (152; 154) coupled in parallel between the internal supply rail (170) and the global supply rail (160). Each cluster (140) of switches (152; 154) has a first switch (152) having a first size and a second switch (154) having a second size, a fault-free first switch (152) having a higher resistance than a fault-free second switch (154). The IC (100) further comprises a test arrangement for testing the respective clusters (140) of switches (152; 154) in a test mode. The test arrangement comprises a test control input; a test output coupled to the respective internal supply rails (170) and control means (110, 114, 116) coupled to the test control input for enabling a selected cluster (140) of switches (152; 154) in the test mode. The control means comprise first selection means (114) for selectively enabling the first switch (152) and second selection means (116) for selectively enabling the second switch (154) of the selected cluster (140) in the test mode. This arrangement allows for the accurate measurement of the resistance of power switches (152; 154) between a global power rail (160) and an internal power rail (170) of a circuit portion (130), thus facilitating the detection of both resistive and stuck-at faults in these switches (152; 154).
摘要翻译：公开了一种集成电路（100），其包括多个电路部分（130），每个电路部分具有经由开关（152）的簇（140）耦合到全局电源轨（160）的内部电源轨（170） ; 154），其并联连接在所述内部供应轨道（170）和所述全局供应轨道（160）之间。开关（152; 154）的每个簇（140）具有具有第一尺寸的第一开关（152）和具有第二尺寸的第二开关（154），无故障的第一开关（152）具有比无故障的第二开关（154）。 IC（100）还包括用于在测试模式下测试开关（152; 154）的相应簇（140）的测试装置。测试装置包括测试控制输入; 耦合到相应的内部电源轨（170）的测试输出和耦合到测试控制输入的控制装置（110,114,116），用于在测试模式下启用所选择的开关（152; 154）的集群（140）。控制装置包括用于选择性地启用第一开关（152）和第二选择装置（116）的第一选择装置（114），用于在测试模式中选择性地启用所选择的集群（140）的第二开关（154）。这种布置允许精确测量电路部分（130）的全局电力轨道（160）和内部电力轨道（170）之间的电力开关（152; 154）的电阻，从而有助于电阻和这些开关（152; 154）中存在故障。

3. 发明授权

US07446559B2 Method and system for powering an integrated circuit 有权
标题翻译：为集成电路供电的方法和系统
公开(公告)号：US07446559B2
公开(公告)日：2008-11-04
申请号：US10576570
申请日：2004-10-18
申请人： Emmanuel Alie
发明人： Emmanuel Alie
IPC分类号： H03K17/16 , G05F1/10
CPC分类号： G06F1/26
摘要： Consistent with an example embodiment, there is a method is for powering an integrated circuit. An integrated circuit comprises a chip within a package assembly, the chip includes a plurality of logic circuits each having at least one power input which should not receive a power voltage exceeding a predetermined maximum operating voltage. The method comprises measuring a power voltage supplied to the integrated circuit directly within the chip at the power input of at least one logic circuit. The power voltage is regulated such that the voltage supplied to the power input of at least one logic circuit of the chip is equal to the predetermined maximum operating voltage of this logic circuit.
摘要翻译：与示例性实施例一致，存在用于为集成电路供电的方法。集成电路包括封装组件内的芯片，芯片包括多个逻辑电路，每个逻辑电路具有至少一个不应接收超过预定最大工作电压的电源电压的电源输入。该方法包括在至少一个逻辑电路的功率输入端测量在芯片内直接提供给集成电路的电源电压。调节电源电压，使得提供给芯片的至少一个逻辑电路的电源输入的电压等于该逻辑电路的预定最大工作电压。

4. 发明授权

US08327108B2 Slave and a master device, a system incorporating the devices, and a method of operating the slave device 有权
标题翻译：从设备和主设备，结合设备的系统以及操作从设备的方法
公开(公告)号：US08327108B2
公开(公告)日：2012-12-04
申请号：US12096165
申请日：2006-10-20
申请人： Daineche Layachi , Emmanuel Alie , Laurent Capella
发明人： Daineche Layachi , Emmanuel Alie , Laurent Capella
IPC分类号： G06F12/00 , G06F13/40
CPC分类号： G06F9/3879 , G06F9/30036
摘要： An electronic slave device includes a hardware data packing block having a configurable multiplexing unit having inputs connected to system bus, wires for receiving in parallel each bit of a data word, outputs connected to the respective data write pins of a memory for outputting in parallel each bit of a rearranged data word to be recorded, and rearrangeable connections between the inputs and the outputs according to a set configuration; a format register, the value of which can be set by an external master device to at least two different values; and a logic circuit capable of setting the connections of the multiplexing unit according to the value of the format register to obtain a rearranged data word having at least one symbol with a shifted position in comparison with the position of this symbol in the received data word.
摘要翻译：电子从设备包括硬件数据打包块，其具有可配置复用单元，其具有连接到系统总线的输入，并行地并行接收数据字的每一位的输出，连接到存储器的相应数据写入引脚的输出，每个要记录的重新排列的数据字的位，以及根据设置的配置的输入和输出之间的可重排连接; 格式寄存器，其值可以由外部主设备设置为至少两个不同的值; 以及逻辑电路，其能够根据格式寄存器的值来设置多路复用单元的连接，以获得与接收的数据字中的该符号的位置相比具有移位位置的至少一个符号的重新排列的数据字。

5. 发明申请

US20100070719A1 SLAVE AND A MASTER DEVICE, A SYSTEM INCORPORATING THE DEVICES, AND A METHOD OF OPERATING THE SLAVE DEVICE 有权
标题翻译：从属和主设备，兼容设备的系统以及操作从设备的方法
公开(公告)号：US20100070719A1
公开(公告)日：2010-03-18
申请号：US12096165
申请日：2006-10-20
申请人： Daineche Layachi , Emmanuel Alie , Laurent Capella
发明人： Daineche Layachi , Emmanuel Alie , Laurent Capella
IPC分类号： G06F13/00 , G06F12/02
CPC分类号： G06F9/3879 , G06F9/30036
摘要： The electronic slave device (6) comprises a hardware data packing block having: • a configurable multiplexing unit (44) having inputs connected to system bus (8) wires for receiving in parallel each bit of a data word, outputs connected to the respective data write pins of a memory (18) for outputting in parallel each bit of a rearranged data word to be recorded, and rearrangeable connections between the inputs and the outputs according to a set configuration; • a format register (40), the value of which can be set by an external master device (4) to at least two different values; and • a logic circuit (48) capable of setting the connections of the multiplexing unit (44) according to the value of the format register (40) to obtain a rearranged data word having at least one symbol with a shifted position in comparison with the position of this symbol in the received data word.
摘要翻译：电子从设备（6）包括硬件数据打包块，其具有：•可配置复用单元（44），其具有连接到系统总线（8）的输入，用于并行地接收数据字的每个位，连接到相应数据的输出写入存储器（18）的引脚，用于并行输出要记录的重新排列的数据字的每个位，以及根据设置的配置的输入和输出之间的可重排连接; •格式寄存器（40），其值可由外部主设备（4）设置为至少两个不同的值; 能够根据格式寄存器（40）的值来设置多路复用单元（44）的连接的逻辑电路（48），以获得具有至少一个具有移位位置的符号的重排数据字，该符号在接收数据字中的位置。

6. 发明授权

US07596774B2 Hard macro with configurable side input/output terminals, for a subsystem 有权
标题翻译：具有可配置的侧面输入/输出端子的硬宏，用于子系统
公开(公告)号：US07596774B2
公开(公告)日：2009-09-29
申请号：US11576685
申请日：2005-09-21
申请人： Caroline Carin , Emmanuel Alie
发明人： Caroline Carin , Emmanuel Alie
IPC分类号： G06F17/50 , G06F7/38 , H03K19/00
CPC分类号： G06F15/7832
摘要： A hard macro device (HMD), for a subsystem (TMi) such as a data processor, comprises a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time critical input data to be processed and at least one time critical output terminal (COT) adapted to deliver time critical output data it has processed. The processing core (C) is surrounded at least partly by a connecting interface zone (CIZ) comprising i) at least one input group of at least two time critical auxiliary input terminals (AITj), located at chosen locations and adapted to receive time critical input data to be processed, and/or at least one output group of at least two time critical auxiliary output terminals (AOTk), located at chosen locations and adapted to deliver processed time critical output data, ii) an input connecting means (LO) for connecting each time critical auxiliary input terminal (AITj) of this input group to the time critical input terminal (CIT), and/or iii) an output connecting means (Bk) for connecting the time critical output terminal (COT) to each time critical auxiliary output terminal (AOTk) of this output group.
摘要翻译：用于诸如数据处理器的子系统（TMi）的硬宏设备（HMD）包括设置有至少一个时间关键输入端（CIT）的处理核心（C），其适于将时间关键输入数据馈送到处理的和至少一个时间的关键输出端（COT），其适于传送其处理的时间关键输出数据。所述处理核心（C）至少部分地由连接接口区域（CIZ）包围，所述连接接口区域（CIZ）包括：i）至少两个至少两个时间关键的辅助输入端子（AITj）的至少一个输入组，位于所选择的位置并适于接收时间关键输入数据，和/或至少两个时间关键辅助输出终端（AOTk）的至少一个输出组，位于所选择的位置并且适于提供经过处理的时间关键输出数据，ii）输入连接装置（LO）用于将该输入组的每个关键辅助输入端子（AITj）连接到时间关键输入端子（CIT），和/或iii）用于将时间关键输出端子（COT）连接到每个时间的输出连接装置（Bk）该输出组的关键辅助输出端子（AOTk）。

7. 发明申请

US20070145986A1 Method and system for powering an integrated circuit 有权
标题翻译：为集成电路供电的方法和系统
公开(公告)号：US20070145986A1
公开(公告)日：2007-06-28
申请号：US10576570
申请日：2004-10-18
申请人： Emmanuel Alie
发明人： Emmanuel Alie
IPC分类号： G01R27/08
CPC分类号： G06F1/26
摘要： The method is for powering an integrated circuit, said integrated circuit comprising a chip within a package assembly, said chip comprising a plurality of logic circuits each having at least one power input which should not receive a power voltage exceeding a predetermined maximum operating voltage. The method comprises the steps of:—measuring (in step 98) the power voltage supplied to the integrated circuit directly within the chip at the power input of at least one logic circuit, and—regulating (in step 96) this power voltage such that the voltage supplied to the power input of at least one logic circuit of the chip is equal to the predetermined maximum operating voltage of this logic circuit.
摘要翻译：该方法是为集成电路供电，所述集成电路包括封装组件内的芯片，所述芯片包括多个逻辑电路，每个逻辑电路具有至少一个不应接收超过预定最大工作电压的电源电压的电源输入。该方法包括以下步骤： - 在至少一个逻辑电路的功率输入端测量（在步骤98中）提供给芯片内的集成电路的电源电压，并调节（在步骤96中）该电源电压，使得提供给芯片的至少一个逻辑电路的电源输入的电压等于该逻辑电路的预定最大工作电压。

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