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1. 发明授权

US06553559B2 Method to determine optical proximity correction and assist feature rules which account for variations in mask dimensions 有权
公开(公告)号：US06553559B2
公开(公告)日：2003-04-22
申请号：US09754910
申请日：2001-01-05
申请人： Lars W. Liebmann , Scott Mansfield , Alfred K. Wong
发明人： Lars W. Liebmann , Scott Mansfield , Alfred K. Wong
IPC分类号： G06F1750
CPC分类号： G03F1/36 , G03F7/70441
摘要： Optical proximity correction (OPC) and assist feature rules are generated using a process window (PW) analysis. A reference pitch is chosen and the mask bias is found that optimizes the process window. This can be done using standard process window analysis or through a weighted process window (WPW) analysis which accounts for focus and dose distributions that are expected in a real process. The WPW analysis gives not only the optimum mask bias, but also the center focus and dose conditions for the optimum process centering. A series of other pitches and mask biases are then analyzed by finding the common process window with the reference pitch. For the standard PW analysis, a common process window is found. For the WPW analysis, the WPW is computed at the center focus and dose conditions found for the reference pitch. If mask or lens errors are to be accounted for, then multiple structures can be included in the analysis. Once the common process windows for the mask features of interest have been computed, functional fits to the data can be found. Once the functional forms have been found for each of the OPC parameters, the rules table can be determined by solving for the spacings of interest in the design.

2. 发明授权

US06602728B1 Method for generating a proximity model based on proximity rules 失效
标题翻译：基于接近度规则生成邻近度模型的方法
公开(公告)号：US06602728B1
公开(公告)日：2003-08-05
申请号：US09754920
申请日：2001-01-05
申请人： Lars W. Liebmann , Scott Mansfield , Alfred K. Wong
发明人： Lars W. Liebmann , Scott Mansfield , Alfred K. Wong
IPC分类号： G01R3126
CPC分类号： G03F1/36 , G03F1/68 , G03F7/70441 , G03F7/705
摘要： A method for generating an optical proximity correction (OPC) model includes generating a set of correction rules for a wafer design containing at least one of lines and assist features, determining a set of corrections that need to be made over a range of sizes and spaces of the lines and assist features based on the set of correction rules, and creating an optical proximity correction model for correcting the wafer design based on the set of corrections.
摘要翻译：一种用于产生光学邻近校正（OPC）模型的方法包括为包含线和辅助特征中的至少一个的晶片设计生成一组校正规则，确定需要在一定范围的尺寸和空间上进行的一组校正基于该组校正规则的线和辅助特征，以及基于该校正集创建用于校正晶片设计的光学邻近校正模型。

3. 发明授权

US06578190B2 Process window based optical proximity correction of lithographic images 有权
公开(公告)号：US06578190B2
公开(公告)日：2003-06-10
申请号：US09759013
申请日：2001-01-11
申请人： Richard A. Ferguson , Mark A. Lavin , Lars W. Liebmann , Alfred K. Wong
发明人： Richard A. Ferguson , Mark A. Lavin , Lars W. Liebmann , Alfred K. Wong
IPC分类号： G06F1750
CPC分类号： G03F1/70 , G03F1/36
摘要： A method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate. The method comprises initially providing a mask pattern of a feature to be created on the substrate using the mask. The method then includes establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern. In its preferred embodiment, the feature is an integrated circuit to be lithographically produced on a semiconductor substrate.

4. 发明授权

US06338922B1 Optimized alternating phase shifted mask design 失效
标题翻译：优化交替相移掩模设计
公开(公告)号：US06338922B1
公开(公告)日：2002-01-15
申请号：US09566885
申请日：2000-05-08
申请人： Lars W. Liebmann , Alfred K. Wong
发明人： Lars W. Liebmann , Alfred K. Wong
IPC分类号： G03F900
CPC分类号： G03F7/70425 , G03F1/30
摘要： A method for reducing lens aberrations sensitivity and proximity effects of alternating phase shifted masks is described. The critical features of a chip design layout are first identified. Multiple, narrow phase regions and auxiliary phase transitions, which provide additional opaque features, are then formed alongside the critical features such that a grating pattern of substantially uniform pitch is printed. Together with a complementary trim mask, the circuit pattern so delineated has reduced sensitivity to lens aberrations and proximity effects.
摘要翻译：描述了用于减少交替相移掩模的透镜像差灵敏度和邻近效应的方法。首先确定了芯片设计布局的关键特征。然后，在临界特征旁边形成提供附加的不透明特征的多个窄相位区域和辅助相位转变，使得印刷基本均匀的间距的光栅图案。与互补的修剪掩模一起，如此描绘的电路图案降低了对透镜像差和邻近效应的敏感性。

5. 发明授权

US5932377A Exact transmission balanced alternating phase-shifting mask for photolithography 失效
标题翻译：用于光刻的精确传输平衡交替移相掩模
公开(公告)号：US5932377A
公开(公告)日：1999-08-03
申请号：US28833
申请日：1998-02-24
申请人： Richard A. Ferguson , Lars W. Liebmann , Scott M. Mansfield , David S. O'Grady , Alfred K. Wong
发明人： Richard A. Ferguson , Lars W. Liebmann , Scott M. Mansfield , David S. O'Grady , Alfred K. Wong
IPC分类号： G03F1/30 , G03F9/00
CPC分类号： G03F1/30
摘要： A two-step method for eliminating transmission errors in alternating phase-shifting masks is described. Initially, the design data is selectively biased to provide a coarse reduction in the inherent transmission error between features of different phase, size, shape, and/or location. During fabrication of the mask with the modified data, residual transmission errors are then eliminated via the positioning of the edges of the etched-quartz trenches which define the phase of a given feature to a set location beneath the opaque chrome film. Application of feedback, in which the aerial image of the mask is monitored during the positioning of the etched-quartz edges, provides additional and precise control of the residual transmission error.
摘要翻译：描述了用于消除交替移相掩模中的传输误差的两步法。最初，设计数据被选择性地偏置以提供不同相位，大小，形状和/或位置的特征之间的固有传输误差的粗略减小。在具有修改数据的掩模制造期间，通过将限定给定特征的相位的蚀刻石英沟槽的边缘定位到不透明铬膜下方的设定位置，残留透射误差被消除。在蚀刻石英边缘的定位期间监测掩模的空中图像的反馈的应用提供对残留传输误差的附加且精确的控制。

6. 发明授权

US06596442B1 Asymmetric halftone biasing for sub-grid pattern adjustment 失效
标题翻译：非对称半色调偏压用于子网格图案调整
公开(公告)号：US06596442B1
公开(公告)日：2003-07-22
申请号：US09533831
申请日：2000-03-23
申请人： Alfred K. Wong , Richard A. Ferguson , Lars W. Liebmann
发明人： Alfred K. Wong , Richard A. Ferguson , Lars W. Liebmann
IPC分类号： G03F900
CPC分类号： G03F1/36
摘要： A technique is described, based on concepts of halftone printing, for controlling feature dimensions in a printed image at increments smaller than the smallest addressable unit of the template used to produce that image. Accordingly, photomasks may be fabricated to yield images with sizes differing from a nominal width by increments which are small fractions of the minimum template size or pixel size. A template fabricated according to this technique includes a feature having one or more edges, and a first array and a second array of shapes (protrusions or indentations) disposed on the edges. The first and second arrays have respective segmentation periods; the first and second segmentation periods are different. Each array is formed of a plurality of identical shapes repeating at every corresponding segmentation period, each shape having a predetermined length and a predetermined width. The shapes (protrusions or indentations) in the first array and the second array may have different lengths, in addition to the two arrays having different segmentation periods; a line feature on a template will thus appear asymmetric with respect to both the length and period of the shapes along the edges of the feature.
摘要翻译：基于半色调打印的概念描述了一种技术，用于以小于用于生成该图像的模板的最小可寻址单位的增量来控制打印图像中的特征尺寸。因此，可以制造光掩模以产生具有与标称宽度不同的尺寸的图像，增量是最小模板尺寸或像素尺寸的小部分。根据该技术制造的模板包括具有一个或多个边缘的特征，以及设置在边缘上的第一阵列和第二阵列的形状（突起或凹陷）。第一和第二阵列具有各自的分割周期; 第一和第二分割周期是不同的。每个阵列由在每个相应的分割周期重复的多个相同形状形成，每个形状具有预定长度和预定宽度。除了具有不同分割周期的两个阵列之外，第一阵列和第二阵列中的形状（突起或凹痕）可以具有不同的长度; 因此，模板上的线特征将相对于沿着特征边缘的形状的长度和周期呈现不对称。

7. 发明授权

US6057063A Phase shifted mask design system, phase shifted mask and VLSI circuit devices manufactured therewith 失效
标题翻译：相移掩模设计系统，相移掩模和用其制造的VLSI电路器件
公开(公告)号：US6057063A
公开(公告)日：2000-05-02
申请号：US824700
申请日：1997-04-14
申请人： Lars W. Liebmann , Ioana C. Graur , Young O. Kim , Mark A. Lavin , Alfred K. Wong
发明人： Lars W. Liebmann , Ioana C. Graur , Young O. Kim , Mark A. Lavin , Alfred K. Wong
IPC分类号： G03F1/00 , G06F17/50 , G03F9/00
CPC分类号： G06F17/5068 , G03F1/26
摘要： A process for creating and verifying a design of phase-shifted masks utilizing at least one phase shift region employing a computer-aided design system. A chip design is provided. A phase-shift mask design capable of producing the chip design is created. Features in a design of the phase-shifted mask that require phase shifting are located. Uncolored phase regions are created on opposite sides of the features. Proper phase termination of the phase regions is ensured based upon space constraints of a phase-shifted mask technique utilized. Phases are determined for the phase regions. Whether coloring errors and un-phase-shiftable design features exist is determined. Mask process specific overlaps and expansions are applied to the mask design to prepare designed data levels for mask manufacture. A residual phase edge image removal design is derived.
摘要翻译：利用采用计算机辅助设计系统的至少一个相移区域来创建和验证相移掩模的设计的过程。提供芯片设计。产生了能够产生芯片设计的相移掩模设计。定位需要相移的相移掩模设计中的特征。未着色的相位区域在特征的相对侧上创建。基于所采用的相移掩模技术的空间限制，确保相位区域的正确相位终止。确定相位区域的相位。是否存在着色误差和不相移设计特征。掩模过程特定的重叠和扩展被应用于掩模设计以准备用于掩模制造的设计的数据级。导出残留相边缘图像去除设计。

8. 发明授权

US08516403B2 Multiple patterning layout decomposition for ease of conflict removal 有权
标题翻译：多重图案化布局分解，便于冲突删除
公开(公告)号：US08516403B2
公开(公告)日：2013-08-20
申请号：US13223844
申请日：2011-09-01
申请人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
发明人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A mechanism is provided for multiple patterning lithography with conflict removal aware coloring. The mechanism makes multiple patterning coloring aware of the conflict removal overhead. The coloring solution explicitly considers ease of conflict removal as one of the coloring objectives. The mechanism pre-computes how much shapes can move in each direction. The mechanism generates a conflict graph where nodes represent shapes in the layout and edges represent conflicts between shapes. The mechanism assigns weights to edges based on available spatial slack between conflicting features. The mechanism then uses the weights to guide multiple patterning coloring. The mechanism prioritizes conflicting features with higher weights to be assigned different colors.
摘要翻译：提供了一种用于具有冲突消除意识着色的多重图案化光刻的机构。该机制使得多个图案化着色意识到冲突移除开销。着色解决方案明确地将冲突移除的容易性作为着色目标之一。该机制预先计算出每个方向上可以移动多少形状。该机制生成一个冲突图，其中节点表示布局中的形状，边缘表示形状之间的冲突。该机制基于冲突特征之间的可用空间松弛来为边缘分配权重。该机构然后使用重量来引导多个图案化着色。该机制优先处理具有较高权重的冲突特征，以分配不同的颜色。

9. 发明授权

US08473885B2 Physical design system and method 失效
公开(公告)号：US08473885B2
公开(公告)日：2013-06-25
申请号：US13413759
申请日：2012-03-07
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

10. 发明授权

US08225255B2 Placement and optimization of process dummy cells 有权
标题翻译：过程虚拟细胞的放置和优化
公开(公告)号：US08225255B2
公开(公告)日：2012-07-17
申请号：US12124472
申请日：2008-05-21
申请人： Xu Ouyang , Geng Han , Lars W. Liebmann
发明人： Xu Ouyang , Geng Han , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G11C29/24 , G06F2217/12 , G11C5/02 , H01L27/0203 , H01L27/105 , Y02P90/265
摘要： A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.
摘要翻译：与存储器阵列的内部存储单元相关地布置处理虚设单元的方法包括：（a）计算存储器阵列的初始处理性能参数; （b）改变电连接到内部单元的层的虚拟单元布局配置; （c）为内部存储单元和改变的布局配置处理虚拟单元应用光刻模拟和屈服模型; 和（d）重复步骤（b）和（c），直到产率最大化。可以进行检查，以确保有足够的空间进行更改，并且对相邻电路没有明显的不利影响。过程性能参数可以是产量或内部存储器单元的处理窗口。

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