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1. 发明授权

US06358790B1 Method of making a capacitor 有权
标题翻译：制作电容器的方法
公开(公告)号：US06358790B1
公开(公告)日：2002-03-19
申请号：US09250501
申请日：1999-02-16
申请人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L218234
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/32136 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/90
摘要： The present invention provides a method for fabricating a capacitor, comprising the steps of forming a trench in a substrate, forming a layer of a first material selected from the group consisting of titanium and titanium nitride in the trench, filling the trench with a conductive material to form a plug, planarizing the substrate, patterning the substrate to expose the first material, forming an electrode material layer over the substrate, and patterning the electrode material layer, whereby the first material is substantially encapsulated by the electrode material layer.
摘要翻译：本发明提供一种制造电容器的方法，包括以下步骤：在衬底中形成沟槽，在沟槽中形成从由钛和氮化钛组成的组中选择的第一材料的层，用导电材料填充沟槽以形成插头，使衬底平坦化，图案化衬底以露出第一材料，在衬底上形成电极材料层，以及图案化电极材料层，由此第一材料基本上被电极材料层封装。

2. 发明授权

US06218255B1 Method of making a capacitor 有权
标题翻译：制作电容器的方法
公开(公告)号：US06218255B1
公开(公告)日：2001-04-17
申请号：US09277778
申请日：1999-03-29
申请人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L2120
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/32136 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/90
摘要： The present invention provides a method for fabricating a capacitor, comprising the steps of forming a trench in a substrate, forming a layer of a first material selected from the group consisting of titanium and titanium nitride in the trench, filling the trench with a conductive material to form a conductive plug, planarizing the substrate, patterning the substrate to partially expose the first material and to create a top portion and a bottom portion to the plug, wherein the bottom portion is in the substrate, and removing the first material from the top portion of the plug.
摘要翻译：本发明提供一种制造电容器的方法，包括以下步骤：在衬底中形成沟槽，在沟槽中形成从由钛和氮化钛组成的组中选择的第一材料的层，用导电材料填充沟槽以形成导电插塞，平坦化基板，图案化基板以部分地暴露第一材料并且产生到插头的顶部部分和底部部分，其中底部部分在基板中，并且从顶部移除第一材料插头的一部分。

3. 发明授权

US06323537B1 Capacitor for an integrated circuit 有权
标题翻译：集成电路电容器
公开(公告)号：US06323537B1
公开(公告)日：2001-11-27
申请号：US09280387
申请日：1999-03-29
申请人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L2900
CPC分类号： H01L28/75 , H01L21/28568 , H01L21/31604 , H01L27/1085 , H01L28/60 , Y10S257/915
摘要： The present invention provides an integrated circuit capacitor comprising a conductive plug comprising a top portion comprising sidewalls, and a bottom portion, wherein the bottom portion of the plug is coated with a material selected from the group consisting of titanium and titanium nitride and wherein the top portion of the plug is substantially not coated with a material selected from the group consisting of titanium and titanium nitride.
摘要翻译：本发明提供了一种集成电路电容器，其包括导电插塞，该导电插塞包括包括侧壁的顶部部分和底部部分，其中插塞的底部涂覆有选自钛和氮化钛的材料，并且其中顶部塞的部分基本上没有被选自钛和氮化钛组成的组中的材料涂覆。

4. 发明授权

US06720604B1 Capacitor for an integrated circuit 有权
标题翻译：集成电路电容器
公开(公告)号：US06720604B1
公开(公告)日：2004-04-13
申请号：US09250500
申请日：1999-02-16
申请人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L2994
CPC分类号： H01L28/75 , H01L21/28568 , H01L27/1085 , H01L28/60
摘要： The present invention provides a capacitor comprising a conductive plug comprising a top surface and exposed sidewalls, wherein the sidewalls comprise a layer selected from the group consisting of titanium and titanium nitride, and an electrode material layer over the conductive plug sidewalls, wherein the layer of electrode material is not titanium nor titanium nitride.
摘要翻译：本发明提供了一种电容器，其包括导电插塞，其包括顶表面和暴露的侧壁，其中所述侧壁包括选自钛和氮化钛的层，以及在导电插塞侧壁上的电极材料层，其中，电极材料不是钛和氮化钛。

5. 发明授权

US06180518B2 Method for forming vias in a low dielectric constant material 有权
标题翻译：在低介电常数材料中形成通孔的方法
公开(公告)号：US06180518B2
公开(公告)日：2001-01-30
申请号：US09430226
申请日：1999-10-29
申请人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy , Pradip Kumar Roy
发明人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy , Pradip Kumar Roy
IPC分类号： H01L214763
CPC分类号： H01L21/02063 , H01L21/31138 , H01L21/76802 , H01L21/76814 , H01L21/76831
摘要： A method for making a semiconductor device includes the steps of forming a first conductive layer adjacent a substrate, forming an etch stop layer on the conductive layer, and forming a dielectric layer on the etch stop layer. The dielectric layer includes a material having a low dielectric constant, and a via is formed through the dielectric layer to expose the etch stop layer at the bottom, with porous sidewalls being produced. The exposed etch stop layer is etched using an etchant that cooperates with etched material from the etch stop layer to form a polymeric layer to coat the porous sidewalls of the via. Since the etchant cooperates with the etched material from the etch stop layer to form the polymeric layer coating the porous sidewalls of the via, a separate coating layer deposition step is not required after the via is etched and cleaned. After the porous sidewalls have been coated and polymeric material has been etched from the bottom of the via, a barrier metal layer is formed on the polymeric layer, a seed layer is formed on the barrier metal layer, and a second conductive layer is formed on the seed layer contacting the first conductive layer in the via.
摘要翻译：制造半导体器件的方法包括以下步骤：在衬底附近形成第一导电层，在导电层上形成蚀刻停止层，并在蚀刻停止层上形成介电层。电介质层包括具有低介电常数的材料，并且通过介电层形成通孔以暴露底部的蚀刻停止层，产生多孔侧壁。使用与蚀刻停止层的蚀刻材料配合的蚀刻剂来蚀刻暴露的蚀刻停止层，以形成聚合物层以涂覆通孔的多孔侧壁。由于蚀刻剂与来自蚀刻停止层的蚀刻材料配合以形成涂覆通孔的多孔侧壁的聚合物层，在蚀刻和清洁通孔之后不需要单独的涂层沉积步骤。在已经涂覆多孔侧壁并且已经从通孔的底部蚀刻聚合物材料之后，在聚合物层上形成阻挡金属层，在阻挡金属层上形成种子层，并且在第二导电层上形成第二导电层种子层与通孔中的第一导电层接触。

6. 发明授权

US06585830B2 Method for cleaning tungsten from deposition wall chambers 失效
公开(公告)号：US06585830B2
公开(公告)日：2003-07-01
申请号：US09727326
申请日：2000-11-30
申请人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy
发明人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy
IPC分类号： B08B500
CPC分类号： C23C16/4405
摘要： An unwanted tungsten film deposit on a Chemical Vapor Deposition chamber is cleaned by adding a mixture of at least two cleaning gases into the chamber at a predetermined temperature and pressure and in contact with said chamber walls for a sufficient length of time. The cleaning gases and reacted tungsten species are removed from the chamber by vacuum, and unreacted cleaning gases are removed by purging the chamber with an inert gas. At least one cleaning gas is selected from the group consisting of bromomethane, dibromomethane, bromoform and mixtures thereof. The temperature of the chamber is preferably at least about 300 degrees Celsius. The cleaning gases in the chamber are at a pressure in the range from about 100 to 200 Torr and the chamber is purged at a pressure in the range from about 200 to 500 Torr.

7. 发明授权

US06727588B1 Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics 有权
标题翻译：集成电路金属间介质中的防扩散阻挡层
公开(公告)号：US06727588B1
公开(公告)日：2004-04-27
申请号：US09377386
申请日：1999-08-19
申请人： Mahjoub Ali Abdelgadir , Nace Layadi , Sailesh Mansinh Merchant , Vivek Saxena , Pei H. Yih
发明人： Mahjoub Ali Abdelgadir , Nace Layadi , Sailesh Mansinh Merchant , Vivek Saxena , Pei H. Yih
IPC分类号： H01L2348
CPC分类号： H01L23/5329 , H01L21/76829 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit by may be fabricated by disposing the diffusion-preventing barrier layer between a first dielectric layer and the conductive layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiOx, where x is preferably less than 2.
摘要翻译：可以防止杂质在低介电常数材料中迁移的帽或阻挡层，从而防止杂质在多级集成电路结构的后续级别中侵袭导电元件。集成电路可以通过在集成电路的上层设置第一介电层和导电层之间设置防扩散阻挡层来制造。扩散防止阻挡层可以在含杂质的电介质材料上的原位形成，随后在其上布置金属层，并且进一步处理多层电介质结构以包括抛光。帽或阻挡层的原位沉积防止了含杂质层暴露于大气中，从而避免了由吸湿，吸氢等引起的层的污染。在示例性实施例中，防扩散阻挡层是含有氧化硅或富硅氧化硅SiO x的材料，其中x优选小于2。

8. 发明授权

US06730600B2 Method of dry etching a semiconductor device in the absence of a plasma 有权
标题翻译：在不存在等离子体的情况下干法蚀刻半导体器件的方法
公开(公告)号：US06730600B2
公开(公告)日：2004-05-04
申请号：US10259256
申请日：2002-09-27
申请人： Nace Layadi , Simon John Molloy , Sailesh Mansinh Merchant , Isik C. Kizilyalli
发明人： Nace Layadi , Simon John Molloy , Sailesh Mansinh Merchant , Isik C. Kizilyalli
IPC分类号： H01L21465
CPC分类号： H01L21/32135 , C23F1/12
摘要： A method for dry etching a material deposited on semiconductor device is performed by chemically reacting the material with an etchant gas. The etching process is conducted in a reaction chamber at a predetermined temperature and predetermined pressure within the reaction chamber and without the need of generating a plasma within the chamber or applying an electrical bias to the semiconductor device. A sufficient amount of gas is introduced into the reaction chamber to selectively remove the material from the semiconductor device.
摘要翻译：通过使材料与蚀刻剂气体化学反应来进行用于干蚀刻沉积在半导体器件上的材料的方法。蚀刻工艺在反应室内以预定温度和预定压力在反应室内进行，而不需要在室内产生等离子体或向半导体器件施加电偏压。将足够量的气体引入反应室以选择性地从半导体器件中去除材料。

9. 发明授权

US06204186B1 Method of making integrated circuit capacitor including tapered plug 有权
标题翻译：制造集成电路电容器包括锥形插头的方法
公开(公告)号：US06204186B1
公开(公告)日：2001-03-20
申请号：US09364366
申请日：1999-07-30
申请人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
发明人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L21311
CPC分类号： H01L28/60 , H01L21/76804 , H01L27/10808 , H01L27/10852 , H01L28/40
摘要： A method of making a capacitor includes the steps of forming an interconnection line above a substrate, depositing a first dielectric layer on the interconnection line, and etching a via in the first dielectric layer. The via has a tapered width which increases in a direction toward the substrate. Further, the method includes filling the via with a conductive metal to form a metal plug, and etching a trench in the first dielectric layer around an upper portion of the metal plug. The metal plug has a tapered width which secures it into the dielectric layer. A second dielectric layer is deposited adjacent the metal plug and an upper electrode is deposited on the second dielectric layer. Preferably, a lower electrode is deposited to line the trench and contact the metal plug.
摘要翻译：一种制造电容器的方法包括以下步骤：在衬底上形成互连线，在互连线上沉积第一介电层，以及蚀刻第一介电层中的通孔。通孔具有朝向基板的方向增加的锥形宽度。此外，该方法包括用导电金属填充通孔以形成金属插塞，并且在金属插塞的上部周围蚀刻第一电介质层中的沟槽。金属插头具有将其固定到电介质层中的锥形宽度。第二电介质层沉积在金属插塞附近，并且上电极沉积在第二电介质层上。优选地，沉积下电极以对准沟槽并接触金属插塞。

10. 发明授权

US06249016B1 Integrated circuit capacitor including tapered plug 有权
标题翻译：集成电路电容器包括锥形插头
公开(公告)号：US06249016B1
公开(公告)日：2001-06-19
申请号：US09364603
申请日：1999-07-30
申请人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
发明人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L28/40
摘要： An integrated circuit capacitor includes a first dielectric layer adjacent a substrate and having a trench therein, and a metal plug comprising an upper portion extending upwardly into the trench, and a lower portion disposed in the first dielectric layer. The lower portion has a tapered width which increases in a direction toward the substrate to thereby secure the metal plug in the dielectric layer. Preferably, the upper portion is also tapered. Furthermore, a second dielectric layer is adjacent the metal plug with an upper electrode thereon.
摘要翻译：集成电路电容器包括与衬底相邻并且在其中具有沟槽的第一电介质层和包括向上延伸到沟槽中的上部的金属插塞和设置在第一电介质层中的下部。下部具有朝向基板的方向增加的锥形宽度，从而将金属塞固定在电介质层中。优选地，上部也是锥形的。此外，第二电介质层与其上的上电极邻近金属插塞。

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