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1. 发明授权

US06232232B1 High selectivity BPSG to TEOS etchant 失效
标题翻译：高选择性BPSG至TEOS蚀刻剂
公开(公告)号：US06232232B1
公开(公告)日：2001-05-15
申请号：US09056323
申请日：1998-04-07
申请人： Whonchee Lee , Kevin J. Torek
发明人： Whonchee Lee , Kevin J. Torek
IPC分类号： H01L21465
CPC分类号： C03C15/00 , H01L21/31111
摘要： An organic acid/fluoride-containing solution etchant having high selectivity for BPSG to TEOS. In an exemplary situation, a TEOS layer may be used to prevent contamination of other components in a semiconductor device by the boron and phosphorous in a layer of BPSG deposited over the TEOS layer. The etchant of the present invention may be used to etch desired areas in the BPSG layer, wherein the high selectivity for BPSG to TEOS of etchant would result in the TEOS layer acting as an etch stop. A second etch with a known etchant may be utilized to etch the TEOS layer. The known etchant for the second etch can be less aggressive and, thus, not damage the components underlying the TEOS layer.
摘要翻译：具有对BOSG对TEOS具有高选择性的有机含酸/氟化物溶液蚀刻剂。在示例性情况下，可以使用TEOS层来防止在沉积在TEOS层上的BPSG层中的硼和磷对半导体器件中的其它部件的污染。本发明的蚀刻剂可用于蚀刻BPSG层中的所需区域，其中对于蚀刻剂的BPSG至TEOS的高选择性将导致TEOS层用作蚀刻停止层。可以使用具有已知蚀刻剂的第二蚀刻来蚀刻TEOS层。用于第二蚀刻的已知蚀刻剂可以较不具有侵蚀性，因此不会损坏TEOS层下面的部件。

2. 发明授权

US06178972B2 Method and apparatus for manufacturing a semiconductor integrated circuit 失效
公开(公告)号：US06178972B2
公开(公告)日：2001-01-30
申请号：US08457686
申请日：1995-06-01
申请人： Shigeru Harada , Takashi Yamashita , Noriaki Fujiki , Tsutomu Tanaka
发明人： Shigeru Harada , Takashi Yamashita , Noriaki Fujiki , Tsutomu Tanaka
IPC分类号： H01L21465
CPC分类号： H01L21/768 , H01L21/02063 , H01L23/53223 , H01L23/53257 , H01L2924/0002 , Y10S438/906 , Y10S438/963 , H01L2924/00
摘要： A method and an apparatus for manufacturing a semiconductor integrated circuit in which semiconductor elements (2) and a wiring structure connecting the semiconductor elements (2) one another are located on a semiconductor substrate (1). In the method or apparatus, a series of wiring elements (4,6,7,9,10), each of which constructs the wiring structure is formed sequentially, then the semiconductor integrated circuit under manufacturing process is washed by neutral solution containing oxidant during the process of forming of the wiring elements (4,6,7,9,10).

3. 发明授权

US06743720B2 Method of manufacturing a portion of a memory by selectively etching to remove metal nitride or metal oxynitride extrusions 失效
标题翻译：通过选择性蚀刻以除去金属氮化物或金属氮氧化物挤出物来制造存储器的一部分的方法
公开(公告)号：US06743720B2
公开(公告)日：2004-06-01
申请号：US10405351
申请日：2003-04-01
申请人： Gary Chen , Li Li , Yongjun Jeff Hu
发明人： Gary Chen , Li Li , Yongjun Jeff Hu
IPC分类号： H01L21465
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/28247 , H01L21/32134
摘要： Metal nitride and metal oxynitride extrusions often form on metal suicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.
摘要翻译：金属氮化物和金属氮氧化物挤出物通常在金属硅化物上形成。这些挤压可能导致短路并降低加工产量。本发明公开了一种选择性地去除这种挤出物的方法。在一个实施方案中，包含氧化剂和螯合剂的新型湿蚀刻选择性地从存储器阵列中的字线除去挤出物。在另一个实施方案中，湿蚀刻包括调节蚀刻的pH以选择性地相对于字线中的其它物质去除某些挤出物的碱。因此，可以使用新的金属硅化物结构来形成新颖的字线和其他类型的集成电路。

4. 发明授权

US06730600B2 Method of dry etching a semiconductor device in the absence of a plasma 有权
标题翻译：在不存在等离子体的情况下干法蚀刻半导体器件的方法
公开(公告)号：US06730600B2
公开(公告)日：2004-05-04
申请号：US10259256
申请日：2002-09-27
申请人： Nace Layadi , Simon John Molloy , Sailesh Mansinh Merchant , Isik C. Kizilyalli
发明人： Nace Layadi , Simon John Molloy , Sailesh Mansinh Merchant , Isik C. Kizilyalli
IPC分类号： H01L21465
CPC分类号： H01L21/32135 , C23F1/12
摘要： A method for dry etching a material deposited on semiconductor device is performed by chemically reacting the material with an etchant gas. The etching process is conducted in a reaction chamber at a predetermined temperature and predetermined pressure within the reaction chamber and without the need of generating a plasma within the chamber or applying an electrical bias to the semiconductor device. A sufficient amount of gas is introduced into the reaction chamber to selectively remove the material from the semiconductor device.
摘要翻译：通过使材料与蚀刻剂气体化学反应来进行用于干蚀刻沉积在半导体器件上的材料的方法。蚀刻工艺在反应室内以预定温度和预定压力在反应室内进行，而不需要在室内产生等离子体或向半导体器件施加电偏压。将足够量的气体引入反应室以选择性地从半导体器件中去除材料。

5. 发明授权

US06616510B2 Chemical mechanical polishing method for copper 有权
公开(公告)号：US06616510B2
公开(公告)日：2003-09-09
申请号：US09735323
申请日：2000-12-12
申请人： Chia-Lin Hsu , Teng-Chun Tsai , Yung-Tsung Wei , Ming-Sheng Yang
发明人： Chia-Lin Hsu , Teng-Chun Tsai , Yung-Tsung Wei , Ming-Sheng Yang
IPC分类号： H01L21465
CPC分类号： H01L21/3212 , B24B37/044 , C09G1/02
摘要： A chemical-mechanical polishing method for polishing a copper oxide layer and a copper layer. The copper oxide layer above the copper layer is first polished using an aqueous solution having a high concentration of polishing particles/chelating agent. The copper layer is then polished using a polishing slurry having a low concentration of polishing particles/chelating agent or the polishing slurry free of polishing particles/chelating agent. Alternatively, the copper oxide layer is polished using a mixture of the aqueous solution and the polishing slurry. After the copper oxide layer is removed, the copper layer is polished using the polishing slurry alone.

6. 发明授权

US06713380B2 Methods for dry etching at low substrate temperatures using gas chemistry including a fluorocarbon gas and a gas including oxygen 失效
标题翻译：使用包括碳氟化合物气体和包括氧气在内的气体化学的低基板温度进行干蚀刻的方法
公开(公告)号：US06713380B2
公开(公告)日：2004-03-30
申请号：US10146865
申请日：2002-05-16
申请人： Takashi Kokubu
发明人： Takashi Kokubu
IPC分类号： H01L21465
CPC分类号： H01J37/32082 , H01J37/3266 , H01L21/28518 , H01L21/31116 , H01L21/76802
摘要： Methods for fabricating semiconductor devices are described, including methods which improve an etching selection ratio of a film to be etched against metal silicide, Si, and photoresist. One method for fabricating a semiconductor device includes the steps of forming Ti silicide films 9a-9c on the gate electrode 3 and the diffusion layers 6 and 7 of source/drain regions, forming an interlayer dielectric film 10 on the Ti silicide films, and dry-etching the interlayer dielectric film to form in the interlayer dielectric film 10 a contact hole 10a located above the gate electrode, and contact holes 10b and 10c located above the diffusion layers of the source/drain regions, wherein etching gas used for the dry-etching is gas including at least fluorocarbon gas and one of O2 gas and O3 gas, and the temperature of the semiconductor substrate is 30° C. or lower when the dry-etching is conducted.
摘要翻译：描述了用于制造半导体器件的方法，包括提高要蚀刻的膜与金属硅化物，Si和光刻胶的蚀刻选择比的方法。制造半导体器件的一种方法包括以下步骤：在栅极电极3上形成Ti硅化物膜9a-9c，在源极/漏极区域形成扩散层6和7，在Ti硅化物膜上形成层间电介质膜10，并干燥在层间电介质膜10中形成位于栅电极上方的接触孔10a，以及位于源/漏区的扩散层上方的接触孔10b和10c，其中用于干 - 蚀刻是至少包含氟碳化合物气体和O 2气体和O 3气体中的一种的气体，当进行干法蚀刻时，半导体衬底的温度为30℃以下。

7. 发明授权

US06184104B2 Alignment mark strategy for oxide CMP 失效
标题翻译：氧化物CMP的对准标记策略
公开(公告)号：US06184104B2
公开(公告)日：2001-02-06
申请号：US09151158
申请日：1998-09-10
申请人： Juan Boon Tan , Soon Ee Neoh
发明人： Juan Boon Tan , Soon Ee Neoh
IPC分类号： H01L21465
CPC分类号： G03F9/708 , G03F9/7076 , G03F9/7084 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for generating alignment marks on the scribe lines in which alignment marks are generated only at oxide layers is described. An alignment mark is formed in an oxide layer on a scribe line of a wafer. The alignment mark is lined with a metal layer and filled with a dielectric layer which is planarized. The alignment mark is used in aligning a reticle to pattern the metal layer and is also used in aligning a reticle to pattern the dielectric layer wherein the step of lining the alignment mark with the metal layer protects the alignment mark.
摘要翻译：描述在仅在氧化物层上产生对准标记的划线上产生对准标记的方法。在晶片的划线上的氧化物层中形成对准标记。对准标记衬有金属层，并填充有平坦化的介电层。对准标记用于对准掩模版以图案化金属层，并且还用于对准掩模版以图案化电介质层，其中将对准标记与金属层衬里的步骤保护对准标记。

8. 发明授权

US06175270B1 Method and apparatus for tailored distortion of a signal prior to amplification to reduce clipping 失效
标题翻译：用于在放大之前对信号进行定制失真以减少削波的方法和装置
公开(公告)号：US06175270B1
公开(公告)日：2001-01-16
申请号：US09035213
申请日：1998-03-05
申请人： Giovanni Vannucci
发明人： Giovanni Vannucci
IPC分类号： H01L21465
CPC分类号： H03F1/3241 , H03F2201/3236
摘要： In order to minimize the adverse effects of RF signal nonlinearities during amplification, especially the deleterious effects of signal clipping which may cause uncontrolled out-of-band emissions known as “spectral regrowth”, the specification relates to a device and a method for intentionally distorting a radio frequency (RF) signal in a “tailored manner”, prior to the amplification of the RF signal. The device monitors the amplitude of a RF signal at the inlet of a “tailored” distorter. A modifying signal waveform is generated whenever the amplitude of the monitored RF signal is greater than a threshold value. The RF signal is delayed to account for signal processing time associated with the generation of the modifying signal waveform. The generated modifying signal waveform is then summed with the delayed RF signal, thereby forming an intentionally distorted version of the original RF signal. The distorted signal is conveyed to a RF signal amplifier for amplification. The modifying waveform is chosen so as to reduce the amplitude of the RF signal peak to a value that does not exceed the clipping threshold. Furthermore, the modifying waveform is chosen (“tailored”) to be less harmful than the effects of the clipping distortion it replaces. The modifying waveform may be completely in-band, out-of-band, or have components of each, depending upon the specific implementation and the desired power spectrum. The process is compatible with current predistortion techniques and may used in conjunction with, or in lieu, of signal predistortion.
摘要翻译：为了最小化放大期间RF信号非线性的不利影响，特别是可能导致被称为“频谱再生长”的不受控制的带外发射的信号削波的有害影响，该说明书涉及用于故意扭曲的装置和方法在RF信号的放大之前以“定制的方式”发射射频（RF）信号。该设备监视“定制”变送器入口处的RF信号的幅度。每当所监视的RF信号的幅度大于阈值时，就产生修改信号波形。 RF信号被延迟以考虑与修改信号波形的产生相关联的信号处理时间。所产生的修改信号波形然后与延迟的RF信号相加，从而形成原始RF信号的有意失真的版本。失真的信号被传送到RF信号放大器进行放大。选择修改波形以将RF信号峰值的幅度减小到不超过限幅阈值的值。此外，修改波形被选择（“量化”）比它所替代的限幅失真的影响更小。根据具体实现和期望的功率谱，修改波形可以是完全带内的，带外的，或具有各自的分量。该过程与当前的预失真技术兼容，并且可以与信号预失真联合使用或代替信号预失真。

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